ISL6590 Datasheet, PDF (5/24 Pages) Intersil Corporation – Digital Multi-Phase PWM Controller for Core-Voltage Regulation

ISL6590
Pin Descriptions
PIN NO.
1
PIN NAME
OUTEN
2-7
8, 21, 39, 57
9
VID[0:5]
VDD_CORE
PWRGD
10, 25, 42,
44, 54
11
VDD_IO
MCLK
12
13
14
15, 18, 22,
26, 30, 34
16, 19, 23,
27, 31, 35
17, 20, 24,
28, 32, 36
MDO
MDI
MCS
NDRIVE[1:6]
PWM[1:6]
IDIG[1:6]
29
33, 48, 50,
51
37, 38, 40,
41
43
EXT_Reset
TEST[1:4]
NC
SYSCLK
45
ERR
46
SOC
47
ATRL
49
ATRH
52
SDATA
53
SCLK
55
ATX
56
ARX
58
OSC_OUT
59
OSC_IN
60
PLL_DIG_VSS
PLL Bypass
61
PLL_DIG_VDD
62
PLL_ANA_VSS
63
PLL_ANA_VDD
64
PLL_Filter
65
GND
TYPE
Input
Input
Power
Output
Power
PIN DESCRIPTION
Output enable high input signal used to command the regulator on and a low input signal turns
the regulator off.
Voltage identification (6 bit). Programs Vout regulation voltage.
IC internal core supply voltage (1.8 VDC logic).
Power Good high output signal to indicate the regulator output voltage is within the specified
range. A low signal indicates the voltage is not within range.
IC I/O input supply voltage (3.3 VDC logic).
Output
Output
Input
Output
Output
EEPROM external memory clock, data is clocked out of the IC on the rising edge and data is
clocked into the ISL6580 IC on the falling edge. Compliant with SPI™ EEPROMs.
EEPROM external memory data output. Compliant with SPI EEPROMs.
EEPROM external memory data input. Compliant with SPI EEPROMs.
EEPROM external memory chip select (Active low). Compliant with SPI EEPROMs.
Low side drive signal used to initiate the ISL6580 to turn on the LSFET.
Output PWM performs pulse width modulation which is used to turn on the ISL6580’s power devices.
Input
Input
Output
Current A/D data serial 7-bit digital word (MSB first). The first bit is a start bit (Start = 1). The
remaining 6 bits represent the sampled peak current in the drain of the particular ISL6580
P-Channel HSFET. (IDIG word transmission is triggered by the falling edge of the PWM signal.)
IDIG is an input that is received at SYSCLK/2, normally 66.6MHz.
Voltage identification (6 bit). Programs Vout regulation voltage.
Test pins for part evaluation
N/A
These pins have not been bonded out.
Input/Output System clock which runs at a 133.3MHz rate used to clock the ISL6580. This is generated by the
internal PLL circuit to create a 4x frequency multiply of the OSC_IN frequency.
Input
Serial data transmitted at a 66MHz (or SYSCLK/2) rate. This 6 bit voltage error is feedback into
the control loop and used to regulate the output voltage.
Input
Start of Conversion signal initiated by the ISL6580’s Voltage A/D to create the ERR signal.
Input
Active Transient Response Low input signal from the ISL6580 indicating a voltage overshoot on
the converter output.
Input
Active Transient Response High input signal from the ISL6580 indicating a voltage droop on the
converter output.
Input/Output Controller serial interface for communication, monitoring, and configuration data between the
ISL6580 and ISL6590 controller.
Output
Serial digital bus clock supplied for the 16.67MHz clocking that accompanies SDATA via the
Backside serial bus.
Output Asynchronous Serial Interface Transmit
Input
Asynchronous Serial Interface Receive
Output Only used if part is using a crystal to generate the system clock.
Input
Requires a 33.33MHz oscillator or crystal which is used to generate system clock.
Ground
Input
Digital Ground for the 4X clock multiplier PLL.
Test mode to bypass PLL input to core.
Power _{1.8V power supply for the 4X clock multiplier PLL clock tree driver (1.8 VDC logic).}
Ground Analog Ground for the 4X clock multiplier PLL.
Power 1.8V power supply for the 4X clock multiplier PLL (1.8 VDC logic).
Analog Input Filter cap for PLL.
Ground Paddle IC Ground
5