ISL6590 Datasheet, PDF (16/24 Pages) Intersil Corporation – Digital Multi-Phase PWM Controller for Core-Voltage Regulation

Adjusting The Digital PID
ISL6590
FIGURE 16. DIGITAL PID COMPENSATOR
Frequency response of the digital PID compensator is
determined by the Kp, Ki, Kd factors. These factors are
stored in nonvolatile memory and are loaded in the controller
at power on reset. The system designer sets the PID
compensators frequency response using user interface
software. The designer enters the frequencies of the
desired poles and zeros and user interface software
calculates the Kp, Ki and Kd factors. the software will
calculate and display the frequency response of the
feedback and the closed loop system.
FIGURE 18. SMALL SIGNAL DESIGN WINDOW
FIGURE 17. DESIGN PARAMETER INPUT WINDOW
FIGURE 19. BODE PLOT
F_Z1 = Frequency of first zero
F_Z2 = Frequency of second zero
F_P0 = Gain * frequency of first pole (A _DC*F _P0)
F_P1 = Frequency of second pole
R_P2 = External Resistor used for third pole
C_P2 = External Capacitor used for third pole
F_P2 = 1 / (2 * π* R_P2 * C_P2 )
The software will calculate the frequency response of the
PID controller and the closed loop system as in figures 20
and 21 below.
16
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