ISL6353_14 Datasheet, PDF (5/30 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12 DDR Memory Systems

ISL6353
Pin Descriptions (Continued)
PIN NUMBER
SYMBOL
DESCRIPTION
17
RTN
Output voltage sense return pin. Connect to the ground at desired remote sensing location.
18, 19 ISUMN and ISUMP Inverting and non-inverting input of the transconductance amplifier for current monitoring and OCP.
20
VDD
5V bias power.
21
VIN
Input supply voltage, used for input supply feed-forward compensation.
22
PROG1
The program pin for the voltage regulator I_MAX setting. Refer to Table 6.
23
BOOT1
Connect an MLCC capacitor across the BOOT1 and the PH1 pins. The boot capacitor is charged through an internal
switch connected from the VDDP pin to the BOOT1 pin.
24
UG1
Output of the Phase 1 high-side MOSFET gate driver. Connect the UG1 pin to the gate of the Phase 1 high-side
MOSFET.
25
PH1
Current return path for the Phase 1 high-side MOSFET gate driver. Connect the PH1 pin to the node consisting of
the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 1.
26
GND
This is an electrical ground connection for the IC. Connect this pin to the ground plane of the PCB right next to the
controller or to the exposed pad on the back of the IC using a low impedance path.
27
LG1
Output of the Phase 1 low-side MOSFET gate driver. Connect the LG1 pin to the gate of the Phase 1 low-side
MOSFET.
28
PWM3
PWM output for Phase 3. When PWM3 is pulled to 5V VDD, the controller will disable Phase 3 and allow other
phases to operate.
29
VDDP
Input voltage bias for the internal gate drivers. Connect +5V to the VDDP pin. Decouple with at least 1µF using an
MLCC capacitor to the ground plane close to the IC.
30
LG2
Output of the Phase 2 low-side MOSFET gate driver. Connect the LG2 pin to the gate of the Phase 2 low-side
MOSFET.
31
GND
This is an electrical ground connection for the IC. Connect this pin to the ground plane of the PCB right next to the
controller or to the exposed pad on the back of the IC using a low impedance path.
32
PH2
Current return path for the Phase 2 high-side MOSFET gate driver. Connect the PH2 pin to the node consisting of
the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 2.
33
UG2
Output of the Phase 2 high-side MOSFET gate driver. Connect the UG2 pin to the gate of the Phase 2 high-side
MOSFET.
34
BOOT2
Connect an MLCC capacitor across the BOOT2 and the PH2 pins. The boot capacitor is charged through an internal
switch connected from the VDDP pin to the BOOT2 pin.
35
PROG2
The program pin for the voltage regulator V_BOOT voltage, droop enable/disable and the number of active phases
for PS1 mode.
36
PSI
This pin can be used to set the power state of the controller with external logic signals. By connecting this pin to
ground, the controller will refer only to the power state indicated by the serial communication bus register. If the
pin is connected to a high impedance, the controller will enter the PS1 state. If the pin is connected to a logic high,
the controller will enter the PS2 state.
37
VSET2
This pin is a logic input that can be used in conjunction with VSET1 to program the output voltage of the regulator
with external logic signals. Refer to Table 9. By connecting VSET1 and VSET2 to ground, the controller will refer to
the VID setting indicated by the serial communication bus register.
38
VSET1
This pin is a logic input that can be used in conjunction with VSET2 to program the output voltage of the regulator
with external signals. Refer to Table 9. By connecting VSET1 and VSET2 to ground, the controller will refer to the
VID setting indicated by the serial communication bus register.
39
OVP
An inverter output, latched high for an overvoltage event. It is reset by POR.
40
ADDR
This pin sets the address offset register, range from 0 to 13 (0h to Dh).
-
GND (Bottom Pad) Electrical ground of the IC. Unless otherwise stated, all signals are referenced to the GND pin. Connect this ground
pad to the ground plane through a low impedance path. Recommend use of at least 5 vias to connect to ground
planes in PCB internal layers.
5
September 15, 2011
FN6897.0