ISL6353_14 Datasheet, PDF (12/30 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12 DDR Memory Systems

ISL6353
Vcrm
Master
Clock
Clock1
PWM1
Clock2
PWM2
Clock3
PWM3
VW
COMP
VW
Vcrs1
Vcrs3
Vcrs2
FIGURE 5. R³ MODULATOR OPERATION DURING A LOAD
STEP-UP RESPONSE
The ISL6353 is a multiphase regulator controller implementing
the Intel VR12™ protocol primarily intended for use in DDR
memory regulator applications. It can be programmed for 1-, 2- or
3-phase operation. It uses Intersil’s patented R³ (Robust Ripple
Regulator™) modulator. The R³ modulator combines the best
features of fixed frequency PWM and hysteretic PWM while
eliminating many of their respective shortcomings. Figure 3
conceptually shows the ISL6353 multiphase R³ modulator circuit,
and Figure 4 shows the principle of operation.
A current source flows from the VW pin to the COMP pin, creating
a voltage window set by the resistor between the two pins. This
voltage window is called the VW window in the following
discussion.
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator discharges
the ripple capacitor C_rm with a current source equal to g_mV_o, where
g_m is a gain factor. The C_rm voltage V_crm is a sawtooth waveform
traversing between the VW and COMP voltages. It resets to VW
when it hits COMP, and generates a one-shot master clock signal. A
phase sequencer distributes the master clock signal to the slave
circuits. If the ISL6353 is in 3-phase mode, the master clock signal
will be distributed to the three phases, and the Clock1~3 signals will
be 120° out-of-phase. If the ISL6353 is in 2-phase mode, the
master clock signal will be distributed to Phases 1 and 2, and the
Clock1 and Clock2 signals will be 180° out-of-phase. If the ISL6353
is in 1-phase mode, the master clock signal will be distributed to
Phase 1 only and is the Clock1 signal.
Each slave circuit has its own ripple capacitor C_rs, whose voltage
mimics the inductor ripple current. A g_m amplifier converts the
inductor voltage into a current source to charge and discharge
C_rs. The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges C_rs. When C_rs
voltage V_Crs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges C_rs.
Since the ISL6353 individual phase modulators use a
large-amplitude and noise-free synthesized signal, V_crs, to
determine the pulse width, phase jitter is lower than conventional
hysteretic mode and fixed PWM mode controllers. Unlike
conventional hysteretic mode converters, the ISL6353 has an
error amplifier that allows the controller to maintain 0.5% output
voltage accuracy.
Figure 5 shows the principle of operation during a load step-up
response. The COMP voltage rises after the load step up,
generating master clock pulses more quickly, so PWM pulses
turn on earlier, increasing the effective switching frequency. This
allows for higher control loop bandwidth than conventional fixed
frequency PWM controllers. The VW voltage rises as the COMP
voltage rises, making the PWM pulses wider as well. During load
step-down response, COMP voltage falls. It takes the master
clock circuit longer to generate the next clock signal, so the PWM
pulse is held off until needed. The VW voltage falls as the COMP
voltage falls, reducing the current PWM pulse width. This kind of
behavior gives the ISL6353 excellent load transient response.
The fact that all the phases share the same VW window voltage
also ensures excellent dynamic current balance among phases.
Diode Emulation and Period Stretching
PHASE
UGATE
LGATE
IL
FIGURE 6. DIODE EMULATION OPERATION
ISL6353 can operate in diode emulation (DE) mode to improve
light load efficiency. In DE mode, the low-side MOSFET conducts
when the current is flowing from source to drain and does not
allow reverse current, thus emulating a diode. As Figure 6 shows,
when LGATE is on, the low-side MOSFET carries current, creating
negative voltage on the phase node due to the voltage drop across
the ON-resistance. The ISL6353 monitors the current by
monitoring the phase node voltage. It turns off LGATE when the
phase node voltage reaches zero to prevent the inductor current
from reversing direction and creating unnecessary power loss.
If the load current is light enough, as Figure 6 shows, the inductor
current will reach and stay at zero before the next phase node
pulse, and the regulator is in discontinuous conduction mode
(DCM). If the load current is heavy enough, the inductor current
will never reach 0A, and the regulator is in CCM although the
controller is in DE mode.
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September 15, 2011
FN6897.0