ISL6353_14 Datasheet, PDF (21/30 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12 DDR Memory Systems

ISL6353
Current Monitor
The ISL6353 provides a current monitor function. The IMON pin
outputs a high-speed analog current source that is 1/4 times the
I_sense current.
I_IMON
=
1_--
4
×
I_sen
se
(EQ. 21)
A resistor R_imon is connected to the IMON pin to convert the
IMON pin current to a voltage. The voltage across R_imon is
expressed in Equation 22:
V_Rimon
=
1_--
4
×
I
sen
s
e
×
R_imo
n
(EQ. 22)
Substitution of Equation 14 into Equation 22 gives Equation 23:
V_Rimon
=
---¹-----
4R_i
×
-----------^R----ⁿ----^t--^c--ⁿ----^e---^t-----------
R_ntcn
e
t
+
R_{-----s--u----m---}
N
×
D_-----C_----R_--
N
×
I_o
×
R_imon
(EQ. 23)
Rewriting Equation 23 gives Equation 24:
R_imon
=
V_{----R----i-m-----o----n----}×_-----R_----i---×_----(_---N_----R_{----n----t--c---n---e---t---+-----}R_{----s---u---m-----})
1_--
4
R_ntcn
e
t
×
D
C
R
×
I_o
(EQ. 24)
Substitution of Equation 5 and application of the full load
condition in Equation 24 gives Equation 25:
V_Rimon
×
R_i
×
⎛
⎜
⎝
N
(_---R_{----n---t--c---s----+-----}R_{----n---t--c---})_----×_-----R_----p-
R_ntcs + R_ntc + R_p
+
⎞
R _{s u m⎠⎟}
R_imon
=
-----------------------------------------------------------------------------------------------------------------------
-^14------(--^R----ⁿ---^t---^c--^s----+-----^R----ⁿ----^t--^c---⁾---^×-----^R----^p-
R_ntcs + R_ntc + R_p
×
D
C
R
×
I_oma
x
(EQ. 25)
where I_omax is the full load current.
A capacitor C_imon can be paralleled with R_imon to filter the IMON
pin voltage. The R_imonC_imon time constant is the user’s choice.
The time constant should be long enough such that switching
frequency ripple is removed.
Phase Current Balancing
ISEN3
INTERNAL
TO IC
ISEN2
Phase3
Rs
Cs
Phase2
Rs
Cs
ISEN1
Phase1
Rs
Cs
L3
Rdcr3 _Rpcb3
IL3
L2
Rdcr2 _Rpcb2
Vo
IL2
L1
Rdcr1 _Rpcb1
IL1
FIGURE 12. CURRENT BALANCING CIRCUIT
The ISL6353 monitors individual phase current by monitoring the
ISEN1, ISEN2, and ISEN3 pin voltages. Figure 12 shows the
current balancing circuit recommended for the ISL6353. Each
phase node voltage is averaged by a low-pass filter consisting of
R_s and C_s, and presented to the corresponding ISEN pin. A long
time constant for R_sC_s should be used such that the ISEN
voltages have minimal ripple and represent the DC current
flowing through the inductors. Recommended values are
R_s = 10kΩ and C_s = 0.22µF.
R_s should be routed to the inductor phase-node pad in order to
help eliminate the effect of phase node parasitic PCB DCR.
Equations 26 through 28 give the ISEN pin voltages:
V_ISEN1 = (R_dcr1 + R_pcb1) × I_L1
(EQ. 26)
V_ISEN2 = (R_dcr2 + R_pcb2) × I_L2
(EQ. 27)
V_ISEN3 = (R_dcr3 + R_pcb3) × I_L3
(EQ. 28)
where R_dcr1, R_dcr2 and R_dcr3 are inductor DCR; R_pcb1, R_pcb2
and R_pcb3 are parasitic PCB DCR between the inductor output
pad and the output voltage rail; and I_L1, I_L2 and I_L3 are inductor
average currents.
The ISL6353 will adjust the phase pulse-width relative to the
other phases to make V_ISEN1 = V_ISEN2 = V_ISEN3, thus to achieve
I_L1 = I_L2 = I_L3, when R_dcr1 = R_dcr2 = R_dcr3 and
R_pcb1 = R_pcb2 = R_pcb3.
Using the same components for L1, L2 and L3 will provide a good
match of R_dcr1, R_dcr2 and R_dcr3. Board layout will determine
R_pcb1, R_pcb2 and R_pcb3. Each phase should be as symmetric as
possible in the PCB layout for the power delivery path between
each inductor and the output voltage load, such that
R_pcb1 = R_pcb2 = R_pcb3.
ISEN3
INTERNAL
TO IC
ISEN2
ISEN1
V3p
Phase3
Rs
Rs
Cs
Rs
V2p
Phase2
Rs
Rs
Cs
Rs
V1p
Phase1
Rs
Rs
Cs
Rs
L3 Rdcr3 _Rpcb3
IL3 _V3n
L2 Rdcr2 _{Rpcb2 Vo}
IL2 _V2n
L1 Rdcr1 _Rpcb1
IL1 _V1n
FIGURE 13. DIFFERENTIAL-SENSING CURRENT BALANCING
CIRCUIT
Sometimes, it is difficult to implement a symmetric layout. For
the circuit shown in Figure 12, an asymmetric layout causes
different R_pcb1, R_pcb2 and R_pcb3 resulting in phase current
imbalance. Figure 13 shows a differential-sensing current
balancing circuit recommended for the ISL6353. The current
sensing traces should be routed to the inductor pads so they only
pick up the inductor DCR voltage. Each ISEN pin sees the average
voltage of three sources: its own phase inductor phase-node pad,
21
September 15, 2011
FN6897.0