ISL6353_14 Datasheet, PDF (11/30 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12 DDR Memory Systems

ISL6353
Gate Driver Timing Diagram
PWM
UGATE
t_LGFUGR
t_RU
t_FU
1V
LGATE
1V
t_FL
t_RL
t_UGFLGR
Theory of Operation
Multiphase R³ Modulator
VW
MASTER CLOCK CIRCUIT
MASTER
MASTER ^COMP
CLOCK _Vcrm
CLOCK
Phase
Sequencer
gmVo
Crm
Clock1
Clock2
Clock3
VW
Vcrs1
Crs1
VW
Vcrs2
Crs2
VW
Vcrs3
Crs3
SLAVE CIRCUIT 1
Clock1 S PWM1 ^{Phase1 L1}
Q
R
IL1
gm
SLAVE CIRCUIT 2
Clock2 S PWM2 ^{Phase2 L2}
Q
R
IL2
gm
SLAVE CIRCUIT 3
Clock3 S PWM3 ^{Phase3 L3}
Q
R
IL3
gm
Vo
Co
VW
V_crm
COMP
MASTER
CLOCK
CLOCK1
PWM1
CLOCK2
PWM2
CLOCK3
PWM3
VW
HYSTERETIC
WINDOW
V_crs2 V_crs3
V_crs1
FIGURE 4. R³ MODULATOR OPERATION PRINCIPLES IN
STEADY STATE
FIGURE 3. R³ MODULATOR CIRCUIT
11
September 15, 2011
FN6897.0