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ISL29501 Datasheet, PDF (5/23 Pages) Intersil Corporation – Auto gain control mechanism
ISL29501
Absolute Maximum Ratings
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 4V
Voltage on All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . (-0.3V to VCC) + 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114E) (Note 6) . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Latch-Up (Tested per JESD-78C; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
QFN Package (Notes 4, 5) . . . . . . . . . . . . .
35
1.2
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 3.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. ESD HBM passed 2kV with exception to pins IRQ and SDA, which passed 1kV.
Electrical Specifications Unless otherwise indicated, all the following tables are at DVCC, AVCC and EVCC at 3V, TA = +25°C, Boldface
limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 8) TYP (Note 8) UNIT
SENSOR PARAMETERS
Modulation Frequency
Chip Power Supply
fmod
DVCC, AVCC,
EVCC
Modulation frequency of emitter
4.45 4.5 4.65 MHz
2.7 3.0 3.3
V
Delay From Chip Enable to First Sample
tcen_fs
Note 7
500
µs
Delay between Sleep Mode to Start of First Sample
Quiescent Current - Sleep Mode, DVCC+AVCC+EVCC
Quiescent Current - Shutdown, DVCC+AVCC+EVCC
tsleep_fs
IS-HS
IS-SD
Note 7
CEn = 1; I2C disable; register values are
retained; SS = SDA = SCL = VCC
CEn = 0; I2C enable; register values are
retained; all other functions are disabled
3
µs
2.5
µA
1
µA
Chip Current While Measuring, DVCC+AVCC+EVCC
IDDact
Emitter duty cycle = 50%, 0x90 = 06h,
0x91 = 00h
55
mA
AFE SPECIFICATIONS
Maximum AFE Input Current PDp/PDn
Imax_PD Design recommendation
12.8
µA
Voltage at PDp
VPDp
1.7
V
Voltage at PDn
VPDn
0.75
V
Low Noise Amplifier
LNA
Provides unity gain
1x
N/A
Differential I to V Conversion Range
TIA Gain 0x97[0:1], b0 = 0 and b1 = 0 default
8k
kΩ
Maximum Photodiode Capacitance Recommended
Cmax
Design recommendation
15
pF
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5
FN8681.3
June 29, 2016