ISL29501 Datasheet, PDF (15/23 Pages) Intersil Corporation – Auto gain control mechanism

ISL29501
A random address read operation consists of a two-byte “write”
instruction followed by a register read operation (see Figure 14).
The master performs the following sequence: a START, a chip
identification byte with the R/W bit set to “0”, a register address
byte, a second START and a second chip identification byte with
the R/W bit set to “1”. After each of the three bytes, the
ISL29501 responds with an ACK. While the master continues to
issue the SCL clock, ISL29501 will transmit data bytes as long as
the master responds with an ACK with the 9th clock. The register
address will automatically increment by 1 after ACK so the next
register’s data will come out with succeeding SCL clocks. The
master terminates the Read operation by issuing a STOP
condition following the last bit of the last data byte
(see Figure 14).
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
STOP
FIGURE 11. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT
FROM RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 12. ACKNOWLEDGE RESPONSE FROM RECEIVER
SIGNALS FROM THE
MASTER
SIGNAL AT SDA
SIGNALS FROM THE
ISL29501
S
WRITE
T
A
R
T
CHIP ADDRESS
BYTE WITH R/W = 0
REG ADDRESS
BYTE
S
DATA
BYTE
T
O
P
1 0 1 0 1 A2 A1 0
000 0 0 001
0 00 00 001
A
A
A
C
C
C
K
K
K
FIGURE 13. EXAMPLE BYTE WRITE SEQUENCE
S
S
SIGNALS _T
T
FROM THE _A
A
A
MASTER _R CHIP ADDRESS
REG ADDRESS
R CHIP ADDRESS
C
T ^{BYTE WITH R/W = 0}
BYTE
T BYTE WITH R/W = 1
K
SIGNAL AT SDA 1 0 1 0 1 A2 A1 0 1 1 0 1 0 0 0 0
A
A
SIGNALS FROM
C
C
THE SLAVE
K
K
1 0 1 0 1 A2 A1 1
D7 D6 D5D4 D3 D2D1D0
A
C _{FIRST READ}
K _{DATA BYTE}
FIGURE 14. MULTIBYTE READ SEQUENCE
S
A
T
C
O
K
P
D7 D6D5D4D3D2D1D0
LAST READ
DATA BYTE
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FN8681.3
June 29, 2016