ISL29501 Datasheet, PDF (14/23 Pages) Intersil Corporation – Auto gain control mechanism

ISL29501
Data Outputs
The sensor outputs a wide variety of information that can be
used by the MCU for processing. A list of parameters that can be
obtained from the sensor are identified in the following.
The information can be relied upon by the digital logic to
generate interrupts for quick decision making or used for other
off-chip processing functions.
• Distance information
• Magnitude information
• Raw I and Q values
• Chip junction temperature
• Emitter forward voltage
• Interrupts for proximity and presence detection
• Enable motion computation based on time stamped distance
values
The validity of data can be used to screen interrupts based on
user requirements enabling robust use cases. Details for these
registers are contained in Table 3 on page 20.
Interrupt Controller
The Interrupt controller is a useful block in the digital core of the
ISL29501. The Interrupt controller generates interrupts based on
sensor state. This allows the user to free up the MCU to do other
tasks while measurements are in progress.
Noise Rejection
Electrical AC power worldwide is distributed at either 50Hz or
60Hz and may interfere with sensor operation. The ISL29501
sensor operation compensated for this and rejects these noise
sources.
I²C Serial Interface
The ISL29501 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device being controlled
is the slave. The master always initiates data transfers and provides
the clock for both transmit and receive operations. Therefore, the
ISL29501 operates as a slave device in all applications.
All communication over the I²C interface is conducted by sending
the MSB of each byte of data first. This device supports multibyte
reads.
Chip Identification (Address)
The ISL29501 has an I²C base address of 0xA4.
1
(MSB)
TABLE 2. IDENTIFICATION BYTE FORMAT
0
1
0
1
A2 A1
0
(LSB)
condition. This operation is useful if the master knows the
A2 and A1 Pins
A2 and A1 are address select pins and can be used to select one
of 4 valid chip addresses. A2 and A1 must be set to their correct
logic levels, see I²C Electrical Specifications on page 6 for
details. The LSB Chip Address is the Read/Write bit. The value is
“1” for a Read operation, and “0” for a Write operation
(see Table 2).
A1 and A2 should be tied to DVSS for default operation.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. The SDA state changes during SCL high are reserved for
indicating START and STOP conditions (see Figure 11 on
page 15). On power-up of the ISL29501, the SDA pin is in the
input mode.
All I²C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
ISL29501 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 11). A START condition is ignored
during the power-up sequence.
All I²C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 11). A STOP condition at the end of a read
operation, or at the end of a write operation places the device in
its standby mode.
An ACK (Acknowledge), is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line low to
acknowledge the reception of the eight bits of data (see
Figure 12 on page 15).
The ISL29501 responds with an ACK after recognition of a START
condition followed by a valid identification (a.k.a. I²C address)
byte. The ISL29501 also responds with an ACK after receiving a
data byte of a write operation. The master must respond with an
ACK after receiving a data byte of a read operation.
Write Operation
A Write operation requires a START condition, followed by a valid
identification byte, a valid address byte, a data byte and a STOP
condition. After each of the three bytes, the ISL29501 responds
with an ACK.
STOP conditions that terminate write operations must be sent by
the master after sending at least 1 full data byte and its
associated ACK signal. If a STOP byte is issued in the middle of a
data byte, or before 1 full data byte + ACK is sent, then the
ISL29501 resets itself without performing the write.
Read Operation
A read operation is shown in Figure 14 on page 15. It consists of
a minimum 4 bytes: A START followed by the ID byte from the
master with the R/W bit set to 0, then an ACK followed by a
register address byte. The master terminates the read operation
by not responding with an ACK and then issuing a STOP
current address and desires to read one or more data bytes.
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FN8681.3
June 29, 2016