ISL29501 Datasheet, PDF (19/23 Pages) Intersil Corporation – Auto gain control mechanism

Register Map (Continued)
ADDR
REGISTER NAME ACCESS
SECTION 0.4: INTERRUPT REGISTERS
0x60 Interrupt Control
RW
DEFAULT
0x00
BIT(S)
BIT NAME
2:0 interrupt_ctrl[2:0]
SECTION 0.7: ANALOG CONTROL REGISTERS
0x90 Driver Range
RW
0x06
0x91 Emitter DAC
RW
0xFA
0x92 Driver Control
RW
0x00
0x93
0xA5
0xB0
Threshold DAC
Emitter Offset
Command
Register
RW
0x00
RW
RW
0x10
3:0 driver_s[3:0]
7:0 emitter_current[7:0]
0 driver_thresh_en
7:0 driver_t[7:0]
3:0
Specific codes defined
soft_start
soft_reset
soft_clear
FUNCTION
COMMENT
Select which interrupt mode to be
used.
0: Interrupts disabled
1: Data ready
3: Interrupts disabled
Current DAC scale
Sets the maximum emitter driver 4.5MHz current
(i.e., the peak of the square wave)
Current DAC value
Emitter current calculation: Peak current =
(0x90[3:0])*emitter_current[7:0]/255
Enable threshold DAC
DC current added to signal current
(Register 0x90 & 0x91)
Emitter voltage meas offset
0 - Threshold DAC disabled
1 - Threshold DAC enabled
Double write required to update all bits in this
register.
LSB  0.125V, scales ADC range for 0xE1
measurement
Emulates sample start pin
Resets all registers
Resets internal state machine
Write 0xB0 = 0x49
Write 0xB0 = 0xD7
Write 0xB0 = 0xD1