ISL29501 Datasheet, PDF (21/23 Pages) Intersil Corporation – Auto gain control mechanism

ISL29501
PCB Design Practices
• The use of low inductance components such as chip resistors
and chip capacitors is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid sharp
corners, use rounded corners when possible. Vias in the signal
lines add inductance at high frequency and should be avoided.
This product is sensitive to noise and crosstalk. Precision
analog layout practices can be applied to this chip as well.
• PCB traces greater than 1" begin to exhibit transmission line
characteristics with signal rise/fall times of 1ns or less. High
frequency performance may be degraded for traces greater
than one inch, unless strip line is used.
• Match channel-to-channel analog I/O trace lengths and layout
symmetry. This will minimize propagation delay mismatches.
• Maximize the use of AC decoupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e., no
split planes or PCB gaps under these lines). Place vias in the
signal I/O lines.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as possible.
• When testing use good quality connectors and cables, matching
cable types and keeping cable lengths to a minimum.
• A minimum of two power supply decoupling capacitors are
recommended (1000pF, 0.01µF) and place as close to the
devices as possible. Do not use vias between the capacitor and
the device because vias add unwanted inductance. Larger
capacitors can be farther away from the device. When vias are
required in a layout, they should be routed as far away from
the device as possible.
PCB Layout Considerations
The use of multilayer PCB stack up is recommended to separate
analog and emitter supplies. Placing a power supply plane
located adjacent to the ground plane creates a large capacitance
with little or no inductance. This will minimize ground bounce
and improve power supply noise. The dielectric thickness
separating these layers should be as thin as possible to minimize
capacitive coupling.
It is important that power supplies be bypassed over a wide
range of frequencies. A combination of large and small width
capacitors that self resonate around the modulation frequency
will provide ample suppression of fundamental and harmonics
that can be coupled to the sensor power supplies (check ESR
ratings).
Ensure that photodiode inputs pins (PDp and PDn) have
symmetric and short traces and minimize placing aggressors
around these routes, The guard shields provided on the IC should
help minimize interference.
Ensure that emitter power (EVCC and EVSS) and ground traces
are low resistance paths with a short return path to emitter
ground.
Minimize trace length and vias to minimize inductance and
minimize noise rejection.
The QFN Package Requires Additional PCB
Layout Rules for the Thermal Pad
The thermal pad is electrically connected to V- supply through the
high resistance IC substrate. Its primary function is to provide
heatsinking for the IC. However, because of the connection to the
V1- and V2- supply pins through the substrate, the thermal pad
must be tied to the V- supply to prevent unwanted current flow to
the thermal pad. Maximum AC performance is achieved if the
thermal pad is attached to a dedicated decoupled layer in a
multilayered PC board. In cases where a dedicated layer is not
possible, AC performance may be reduced at upper frequencies.
The thermal pad requirements are proportional to power
dissipation and ambient temperature. A dedicated layer
eliminates the need for individual thermal pad area. When a
dedicated layer is not possible, an isolated thermal pad on
another layer should be used. Pad area requirements should be
evaluated on a case-by-case basis.
For additional information on PCB layout information see
“AN1917, “ISL29501 Layout Design Guide””
General Power PAD Design
Considerations
The following is an example of how to use vias to remove heat
from the IC.
FIGURE 16. PCB VIA PATTERN
We recommend that you fill the thermal pad area with
vias. A typical via array would be to fill the thermal pad footprint
spaced such that they are center-on-center 3x the radius apart
from each other. Keep the vias small, but not so small that their
inside diameter prevents solder wicking through the holes during
reflow.
Connect all vias to the potential outlined in the datasheet for the
pad, typically the ground plane but not always, so check the pin
description. It is important the vias have a low thermal resistance
for efficient heat transfer. Do not use “thermal relief” patterns to
connect the vias. It is important to have a complete connection of
the plated through-hole to each plane.
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FN8681.3
June 29, 2016