ISL29501 Datasheet, PDF (17/23 Pages) Intersil Corporation – Auto gain control mechanism

Register Map
ADDR
REGISTER NAME ACCESS DEFAULT
PAGE 0: CONTROL, SETTING AND STATUS REGISTERS
0x00 Device ID
RO
0xA
0x01 Master Control
RW
0x00
0x02 Status Registers
RO
SECTION 0.1: SAMPLING CONTROL REGISTERS
0x10
Integration Period RW
0x02
2
0x11
0x12
Sample Period
Sample
Period Range
RW
0x00
RW
0x00
0x13 Sample Control
RW
0x7C
0
0
3
1
BIT(S)
BIT NAME
7:0 chip_id[7:0]
0 c_en
0 enout
1 ready
2 vdd ok
FUNCTION
Device ID
Chip enable
‘1’ = Output enabled
‘1’ = Chip ready
‘1’ = Internal power-good
COMMENT
Default to '0A'
Same meaning as CEn pin
0: Enabled (default)
1: Disabled
Internal regular output voltage
3:0 sample_len[3:0] 
Controls the length of for each
Sample_len is also called integration time. This
71.1µs*2^{{sample_len[3:0]}}
sample, which is equal to the time value dictates the number of pulses of the
Maximum = 71.1µs*2¹¹ = 145.6ms during, which the optical pulse is 4.5MHz clock on the EIR pin.
active.
7:0 sample_period[7:0]
Controls the time between the start Sample period = 450µs*(sample_period[7:0]+1)
of each sample
1:0 sample_skip[1:0]
Sample skipping select
0: Sample period multiplied by 2⁰
1: Sample period multiplied by 2¹
2: Sample period multiplied by 2²
3: Sample period multiplied by 2³ (default)
0 adc_mode
1 cali_mode
3:2 cali_freq[1:0]
4 light_en
Single-shot/free running
Calibration vs light order for single
shot mode
Sets frequency of calibration
samples for free running mode
Light sample enable
0: Free running, a single TRIGGER to start is
required
1: Single shot, will only sample off external
trigger
0: Calibration happens before light samples for
single shot mode
1: Calibration happens after light samples for
single shot mode
0: Calibration sample after every 16 light
samples
1: Calibration sample after every 32 light
samples
2: Calibration sample after every 64 light
samples
3: Calibration sample after every 128 light
samples
0: Calibration disabled
1: Calibration enabled