ISL12027 Datasheet, PDF (5/28 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM

ISL12027
Watchdog Timer/Low Voltage Reset Parameters
SYMBOL
PARAMETER
CONDITIONS
t_RPD
t_PURST
V_RVALID
V_DD Detect to RESET LOW
Power-up Reset Time-Out Delay
Minimum V_DD for Valid RESET
Output
V_RESET ISL12027-4.5A Reset Voltage Level
ISL12027 Reset Voltage Level
ISL12027-3 Reset Voltage Level
ISL12027-2.7A Reset Voltage Level
ISL12027-2.7 Reset Voltage Level
t_WDO Watchdog Timer Period
32.768kHz crystal between X1
and X2
t_RST
Watchdog Timer Reset Time-Out 32.768kHz crystal between X1
Delay
and X2
t_RSP I²C Interface Minimum Restart Time
EEPROM SPECIFICATIONS
EEPROM Endurance
EEPROM Retention
Temperature ≤75°C
TYP
MIN (Note 5)
500
100
250
1.0
4.59
4.64
4.33
4.38
3.04
3.09
2.87
2.92
2.58
2.63
1.70
1.75
725
750
225
250
225
250
1.2
>2,000,000
50
MAX
400
4.69
4.43
3.14
2.97
2.68
1.801
775
275
275
UNITS
ns
ms
V
NOTES
9
V
V
V
V
V
s
ms
ms
ms
µs
Cycles
Years
Serial Interface (I²C) Specifications
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
V_IL SDA, and SCL Input Buffer LOW SBIB = 1 (Under V_DD mode)
-0.3
0.3 x V_DD
V
Voltage
V_IH SDA, and SCL Input Buffer HIGH SBIB = 1 (Under V_DD mode)
Voltage
0.7 x V_DD
V_DD + 0.3
V
Hysteresis SDA and SCL Input Buffer
SBIB = 1 (Under V_DD mode)
0.05 x V_DD
V
Hysteresis
V_OL SDA Output Buffer LOW Voltage
I_LI Input Leakage Current on SCL
I_LO I/O Leakage Current on SDA
TIMING CHARACTERISTICS
I_OL = 4mA
V_IN = 5.5V
V_IN = 5.5V
0
0.4
V
0.1
10
µA
0.1
10
µA
f_SCL SCL Frequency
t_IN Pulse Width Suppression Time at Any pulse narrower than the max spec
SDA and SCL Inputs
is suppressed.
400
kHz
50
ns
t_AA SCL Falling Edge to SDA Output SCL falling edge crossing 30% of V_DD,
Data Valid
until SDA exits the 30% to 70% of V_DD
window.
900
ns
t_BUF Time the Bus Must be Free Before SDA crossing 70% of V_DD during a
1300
ns
the Start of a New Transmission STOP condition, to SDA crossing 70%
of V_DD during the following START
condition.
t_LOW Clock LOW Time
Measured at the 30% of V_DD crossing. 1300
ns
t_HIGH Clock HIGH Time
Measured at the 70% of V_DD crossing. 600
ns
NOTES
5
FN8232.4
October 18, 2006