ISL12027 Datasheet, PDF (16/28 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM

ISL12027
V_DD
V_BAT
V_TRIP
V_TRIP
BATTERY BACKUP
MODE
3.0V
2.2V
V_TRIP + V_TRIPHYS
FIGURE 14. BATTERY SWITCHOVER WHEN V_BAT > V_TRIP
OPTION 2 -LEGACY POWER CONTROL MODE
(DEFAULT)
The Legacy Mode follows conditions set in X1226 products.
In this mode, switching from V_DD to V_BAT is simply done by
comparing the voltages and the device operates from
whichever is the higher voltage. Care should be taken when
changing from Normal to Legacy Mode. If the V_BAT voltage is
higher than V_DD, then the device will enter battery back up
and unless the battery is disconnected or the voltage
decreases, the device will no longer operate from V_DD.
To select the Option 2, BSW bit in the Power Register must
be set to “BSW = 1”.
• Normal Mode (V_DD) to Battery Backup Mode (V_BAT)
To transition from the V_DD to V_BAT mode, the following
conditions must be met:
V_DD < V_BAT - V_BATHYS
• Battery Backup Mode (V_BAT) to Normal Mode (V_DD)
The device will switch from the V_BAT to V_DD mode when the
following condition occurs:
V_DD > V_BAT +V_BATHYS
The Legacy Mode power control conditions are illustrated in
Figure 15 below.
V_BAT
V_DD
OFF
VOLTAGE
ON
IN
FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE
Power On Reset
Application of power to the ISL12027 activates a Power On
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
- It prevents the system microprocessor from starting to
operate with insufficient voltage.
- It prevents the processor from operating prior to
stabilization of the oscillator.
- It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
- It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When V_DD exceeds the device V_RESET threshold value for
typically 250ms the circuit releases RESET, allowing the
system to begin operation. Recommended slew rate is
between 0.2V/ms and 50V/ms.
Watchdog Timer Operation
The watchdog timer timeout period is selectable. By writing a
value to WD1 and WD0, the watchdog timer can be set to 3
different time out periods or off. When the Watchdog timer is
set to off, the watchdog circuit is configured for low power
operation. See Table 6.
TABLE 6.
WD1
WD0
DURATION
1
1
1
0
0
1
0
0
disabled
250ms
750ms
1.75s
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of SDA
when the SCL line is high (START condition). The start
signal restarts the watchdog timer counter, resetting the
period of the counter back to the maximum. If another
START fails to be detected prior to the watchdog timer
expiration, then the RESET pin becomes active for one reset
time out period. In the event that the start signal occurs
during a reset time out period, the start will have no effect.
When using a single START to refresh watchdog timer, a
STOP condition should be followed to reset the device back
to stand-by mode. See Figure 3.
Low Voltage Reset (LVR) Operation
When a power failure occurs, a voltage comparator
compares the level of the V_DD line versus a preset threshold
voltage (V_RESET), then generates a RESET pulse if it is
below V_RESET. The reset pulse will timeout 250ms after the
V_DD line rises above V_RESET. If the V_DD remains below
V_RESET, then the RESET output will remain asserted low.
Power-up and power-down waveforms are shown in
Figure 4. The LVR circuit is to be designed so the RESET
signal is valid down to V_DD = 1.0V.
16
FN8232.4
October 18, 2006