ISL12027 Datasheet, PDF (13/28 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM

ISL12027
prevent write operations to one of eight segments of the
array. The partitions are described in Table 3.
TABLE 3.
PROTECTED ADDRESSES
ISL12027
ARRAY LOCK
000
None (Default)
None
001
010
011
100
101
110
111
180_h – 1FF_h
100_h – 1FF_h
000_h – 1FF_h
000_h – 03F_h
000_h – 07F_h
000_h – 0FF_h
000_h – 1FF_h
Upper 1/4
Upper 1/2
Full Array
First 4 Pages
First 8 Pages
First 16 Pages
Full Array
Oscillator Compensation Registers
There are two trimming options.
- ATR. Analog Trimming Register
- DTR. Digital Trimming Register
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64 to +110ppm of total
adjustment.
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34 to
+80ppm to the nominal frequency compensation.
X1
C_X1
X2
C_X2
CRYSTAL
OSCILLATOR
and X2 pins to ground (see Figure 12). The value of C_X1 and
C_X2 is given by the following formula:
CX = (16 ⋅ b5 + 8 ⋅ b4 + 4 ⋅ b3 + 2 ⋅ b2 + 1 ⋅ b1 + 0.5 ⋅ b0 + 9)pF
The effective series load capacitance is the combination of
C_X1 and C_X2:
CLOAD
=
----------------¹------------------
⎛
⎝
-----¹-----
C_X1
+
C^-----1_X^----₂^{-⎠⎞}
CLOAD
=
⎛
⎝
-¹--⁶-----^â‹---^b---⁵----⁺-----⁸----^â‹---^b---⁴-----⁺----⁴----^â‹---^b----³----⁺----²-₂----^â‹---^b---²----⁺----¹-----^â‹---^b---¹----⁺-----⁰---^.-⁵----^â‹----^b---⁰----⁺----⁹--_⎠⎞
p
F
For example, C_LOAD(ATR = 00000) = 12.5pF,
C_LOAD(ATR = 100000) = 4.5pF, and C_LOAD(ATR = 011111) =
20.25pF. The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps.
Note that these are typical values.
DTR Register - DTR2, DTR1, DTR0: Digital
Trimming Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
DTR2 is a sign bit. DTR2 = 0 means frequency
compensation is >0. DTR2 = 1 means frequency
compensation is <0.
DTR1 and DTR0 are scale bits. DTR1 gives 10ppm
adjustment and DTR0 gives 20ppm adjustment.
A range from -30ppm to +30ppm can be represented by
using three bits above.
TABLE 4. DIGITAL TRIMMING REGISTERS
DTR REGISTER
DTR2
DTR1
DTR0
ESTIMATED FREQUENCY
PPM
0
0
0
0
0
1
0
+10
0
0
1
+20
0
1
1
+30
1
0
0
0
1
1
0
-10
1
0
1
-20
1
1
1
-30
FIGURE 12. DIAGRAM OF ATR
The effective on-chip series load capacitance, C_LOAD,
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). C_LOAD is changed via two digitally
controlled capacitors, C_X1 and C_X2, connected from the X1
PWR Register: SBIB, BSW, VTS2, VTS1, VTS0
SBIB: Serial Bus Interface (Enable)
The serial bus can be disabled in battery backup mode by
setting this bit to “1”. This will minimize power drain on the
battery. The Serial Interface can be enabled in battery
backup mode by setting this bit to “0” (default is “0”). See
Reset and Power Control section.
13
FN8232.4
October 18, 2006