ISL12027 Datasheet, PDF (15/28 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM

ISL12027
DWA1 registers, respectively. Those registers will require a
special page write for nonvolatile storage. The
recommended page write sequences are as follows:
1. 16-byte page writes: The best way to write or update the
Alarm Registers is to perform a 16-byte write beginning at
address 0001h (MNA0) and wrapping around and ending
at address 0000h (SCA0). This will insure that non-
volatile storage takes place. This means that the code
must be designed so that the Alarm0 data is written
starting with Minutes register, and then all the Alarm1
data, with the last byte being the Alarm0 Seconds (the
page ends at the Alarm1 Y2k register and then wraps
around to address 0000h).
Alternatively, the 16-byte page write could start with
address 0009h, wrap around and finish with address
0008h. Note that any page write ending at address
0007h or 000Fh (the highest byte in each Alarm) will not
trigger a nonvolatile write, so wrapping around or
overlapping to the following Alarm's Seconds register is
advised.
2. Other nonvolatile writes: It is possible to do writes of
less than an entire page, but the final byte must always
be addresses 0000h through 0004h or 0008h though
000Ch to trigger a nonvolatile write. Writing to those
blocks of 5 bytes sequentially, or individually, will trigger a
nonvolatile write. If the DWA0 or DWA1 registers need to
be set, then enough bytes will need to be written to
overlap with the other Alarm register and trigger the
nonvolatile write. For Example, if the DWA0 register is
being set, then the code can start with a multiple byte
write beginning at address 0006h, and then write 3 bytes
ending with the SCA1 register as follows:
Addr Name
0006h DWA0
0007h Y2K0
0008h SCA1
If the Alarm1 is used, SCA1 would need to have the correct
data written.
Power Control Operation
The power control circuit accepts a V_DD and a V_BAT input.
Many types of batteries can be used with Intersil RTC
products. For example, 3.0V or 3.6V Lithium batteries are
appropriate, and battery sizes are available that can power
an Intersil RTC device for up to 10 years. Another option is
to use a SuperCap for applications where V_DD is interrupted
for up to a month. See the Applications Section for more
information.
There are two options for setting the change-over conditions
from V_DD to Battery back-up mode. The BSW bit in the PWR
register controls this operation.
- Option 1 - Standard Mode
- Option 2 - Legacy Mode (Default)
Note that the I²C bus may or may not be operational during
battery backup, that function is controlled by the SBIB bit.
That operation is covered after the power control section.
OPTION 1- STANDARD POWER CONTROL MODE
In the Standard mode, the supply will switch over to the
battery when V_DD drops below V_TRIP or V_BAT, whichever is
lower. In this mode, accidental operation from the battery is
prevented since the battery backup input will only be used
when the V_DD supply is shut off.
To select Option 1, BSW bit in the Power Register must be
set to “BSW = 0”. A description of power switchover follows.
Standard Mode Power Switchover
• Normal Operating Mode (V_DD) to Battery Backup Mode
(V_BAT)
To transition from the V_DD to V_BAT mode, both of the
following conditions must be met:
• Condition 1:
V_DD < V_BAT - V_BATHYS
where V_BATHYS ≈ 50mV
• Condition 2:
V_DD < V_TRIP
where V_TRIP ≈ 2.2V
• Battery Backup Mode (V_BAT) to Normal Mode (V_DD)
The ISL12027 device will switch from the V_BAT to V_DD mode
when one of the following conditions occurs:
• Condition 1:
V_DD > V_BAT + V_BATHYS
where V_BATHYS ≈ 50mV
• Condition 2:
V_DD > V_TRIP + V_TRIPHYS
where V_TRIPHYS ≈ 30mV
There are two discrete situations that are possible when
using Standard Mode: V_BAT< V_TRIP and V_BAT >V_TRIP.
These two power control situations are illustrated in Figures
13 and 14.
BATTERY BACKUP
V_DD
MODE
V_TRIP
V_BAT
2.2V
1.8V
V_BAT - V_BATHYS
V_BAT + V_BATHYS
FIGURE 13. BATTERY SWITCHOVER WHEN V_BAT < V_TRIP
15
FN8232.4
October 18, 2006