ISL12027 Datasheet, PDF(14/28 Page) Intersil Corporation – Real Time Clock/Calendar with EEPROM

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ISL12027 Datasheet, PDF (14/28 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM

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ISL12027

BSW: Power Control Bit

The Power Control bit, BSW, determines the conditions for

switching between VDD and Back Up Battery. There are two

options.

Option 1. Standard: Set âBSW = 0â

Option 2. Legacy /Default Mode: Set âBSW = 1â

See Power Control Operation later in this document for more

details. Also see âI2C Communications During Battery

backup and LVR Operationâ in the Applications section for

important details.

VTS2, VTS1, VTS0: VRESET Select Bits

The ISL12027 is shipped with a default VDD threshold

(VRESET) per the ordering information table. This register is

a non-volatile with no protection, therefore any writes to this

location can change the default value from that marked on

the package. If not changed with a non-volatile write, this

value will not change over normal operating and storage

conditions. However, ISL12027 has four (4) additional

selectable levels to fit the customers application. Levels are:

4.64V (default), 4.38V, 3.09V, 2.92V and 2.63V. The VRESET

selection is via 3 bits (VTS2, VTS1 and VTS0). See Table 5.

Care should be taken when changing the VRESET select bits.

If the VRESET voltage selected is higher than VDD, then the

device will go into RESET and unless VDD is increased, the

device will no longer be able to communicate using the I2C

bus.

TABLE 5.

VTS2

VTS1

VTS0

VRESET

4.64V

4.38V

3.09V

2.92V

2.63V

Device Operation

Writing to the Clock/Control Registers

Changing any of the bits of the clock/control registers

requires the following steps:

1. Write a 02h to the Status Register to set the Write Enable

Latch (WEL). This is a volatile operation, so there is no

delay after the write. (Operation preceded by a start and

ended with a stop).

2. Write a 06h to the Status Register to set both the Register

Write Enable Latch (RWEL) and the WEL bit. This is also

a volatile cycle. The zeros in the data byte are required.

(Operation proceeded by a start and ended with a stop).

Write all eight bytes to the RTC registers, or one byte to the

SR, or one to five bytes to the control registers. This

sequence starts with a start bit, requires a slave byte of

â11011110â and an address within the CCR and is terminated

by a stop bit. A write to the EEPROM registers in the CCR

will initiate a non-volatile write cycle and will take up to 20ms

to complete. A write to the RTC registers (SRAM) will require

much shorter cycle time (t = tBUF). Writes to undefined areas

have no effect. The RWEL bit is reset by the completion of a

write to the CCR, so the sequence must be repeated to

again initiate another change to the CCR contents. If the

sequence is not completed for any reason (by sending an

incorrect number of bits or sending a start instead of a stop,

for example) the RWEL bit is not reset and the device

remains in an active mode. Writing all zeros to the status

operation occurring between any of the previous operations

will not interrupt the register write operation.

Alarm Operation

Since the alarm works as a comparison between the alarm

registers and the RTC registers, it is ideal for notifying a host

processor of a particular time event and trigger some action

as a result. The host can be notified by polling the Status

Alarm 1 and AL0 for Alarm 0), indicate if an alarm has

happened. The AL1 and AL0 bits in the status register are

reset by the falling edge of the eighth clock of status register

read.

There are two alarm operation modes: Single Event and

periodic Interrupt Mode:

1. Single Event Mode is enabled by setting the AL0E or

AL1E bit to â1â, the IM bit to â0â, and disabling the

frequency output. This mode permits a one-time match

between the alarm registers and the RTC registers. Once

this match occurs, the AL0 or AL1 bit is set to â1â. Once

the AL0 or AL1 bit is read, this will automatically resets it.

Both Alarm registers can be set at the same time to

trigger alarms. Polling the SR will reveal which alarm has

been set.

2. Interrupt Mode (or âPulsed Interrupt Modeâ or PIM) is

enabled by setting the AL0E or AL1E bit to â1â the IM bit

to â1â, and disabling the frequency output. If both AL0E

and AL1E bits are set to 1, then only the AL0E PIM alarm

will function (AL0E overrides AL1E). This means that

once the interrupt mode alarm is set, it will continue to

alarm for each occurring match of the alarm and present

time. This mode is convenient for hourly or daily

hardware interrupts in microcontroller applications such

as security cameras or utility meter reading. Interrupt

Mode CANNOT be used for general periodic alarms,

however, since a specific time period cannot be

programmed for interrupt, only matches to a specific time

of day. The interrupt mode is only stopped by disabling

the IM bit or the Alarm Enable bits.

Writing to the Alarm Registers

The Alarm Registers are non-volatile but require special

attention to insure a proper non-volatile write takes place.

Specifically, byte writes to individual registers are good for all

but registers 0006h and 0000Eh, which are the DWA0 and

FN8232.4

October 18, 2006

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