ISL12027 Datasheet, PDF (23/28 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM

ISL12027
PARAMETER
Frequency
Frequency Tolerance
Turnover Temperature
Operating Temperature Range
Parallel Load Capacitance
Equivalent Series Resistance
TABLE 7. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL RTC’S
MIN
TYP
MAX
UNITS
NOTES
32.768
kHz
±100
ppm
Down to 20ppm if desired
20
25
30
°C
Typically the value used for most crystals
-40
85
°C
12.5
pF
50
kΩ
For best oscillator performance
MANUFACTURER
Citizen
Epson
Raltron
SaRonix
Ecliptek
ECS
Fox
TABLE 8. CRYSTAL MANUFACTURERS
PART NUMBER
TEMP RANGE
CM201, CM202, CM200S
-40 to +85°C
MC-405, MC-406
-40 to +85°C
RSM-200S-A or B
-40 to +85°C
32S12A or B
-40 to +85°C
ECPSM29T-32.768K
-10 to +60°C
ECX-306/ECX-306I
-10 to +60°C
FSM-327
-40 to +85°C
+25°C FREQUENCY TOLERANCE
±20ppm
±20ppm
±20ppm
±20ppm
±20ppm
±20ppm
±20ppm
A final application for the ATR control is in-circuit calibration
for high accuracy applications, along with a temperature
sensor chip. Once the RTC circuit is powered up with battery
backup, and frequency drift is measured. The ATR control is
then adjusted to a setting which minimizes drift. Once
adjusted at a particular temperature, it is possible to adjust at
other discrete temperatures for minimal overall drift, and
store the resulting settings in the EEPROM. Extremely low
overall temperature drift is possible with this method. The
Intersil evaluation board contains the circuitry necessary to
implement this control.
For more detailed operation see Intersil’s application note
AN154 on Intersil’s website at www.intersil.com.
Layout Considerations
The crystal input at X1 has a very high impedance and will
pick up high frequency signals from other circuits on the
board. Since the X2 pin is tied to the other side of the crystal,
it is also a sensitive node. These signals can couple into the
oscillator circuit and produce double clocking or mis-
clocking, seriously affecting the accuracy of the RTC. Care
needs to be taken in layout of the RTC circuit to avoid noise
pickup. Figure 27 shows a suggested layout for the
ISL12027 or ISL12026 devices.
FIGURE 27. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-8
The X1 and X2 connections to the crystal are to be kept as
short as possible. A thick ground trace around the crystal is
advised to minimize noise intrusion, but ground near the X1
and X2 pins should be avoided as it will add to the load
capacitance at those pins. Keep in mind these guidelines for
other PCB layers in the vicinity of the RTC device. A small
decoupling capacitor at the V_DD pin of the chip is mandatory,
with a solid connection to ground (Figure 27).
23
FN8232.4
October 18, 2006