ISL5217_05 Datasheet, PDF (42/43 Pages) Intersil Corporation – Quad Programmable Up Converter

ISL5217
Appendix A -- Errata Sheet
Microprocessor Interface Issue
A Chip Select (CS) operational issue has been identified and
isolated to the design of the pad input circuitry in the write
(WR) input cell. Under certain conditions, the combinational
logic contained in the pads allows an internal chip rising
edge write (WR_To_Core) signal to occur when the external
WR pin is high and the CS pin is transitioned from the
inactive high state to the active low state. The combinational
logic contained in the pads is functionally shown in Figure
29.
If after a completed write cycle to the chip, the WR is again
asserted low while CS is inactive high, as would happen if a
write to another device on the bus occurs, the state of the
control logic in the chip is changed such that the next time
CS is asserted low and WR is inactive high, as would
happen at the start of a chip read cycle, an internal
WR_To_Core strobe will be generated and the chip register
corresponding to the state of the address bus at the time of
the falling edge of CS will be inadvertently loaded with the
data present on the data bus P<15:0>.
Work Arounds
The recommended work around for the device is to place the
status register address (0x016) or any unused address on
the A<6:0>address bus prior to enabling the device with the
CS line. The excess write will then either clear the device’s
status register or perform a “dummy” write to an unused
address space as the chip is enabled. Care should be
utilized when enabling the CS such that the dummy address
remains on the bus until any CS decoding bounces are
complete.
Alternatively, if system considerations allow, on read
operations the WR could be placed in the active low state
prior to CS being asserted active low per Figure 30. This
would be enveloping the CS signal with the WR signal, thus
preventing the extra write from occurring on the falling edge
of CS. Similarly during a write cycle, the WR could be placed
in the active low state prior to CS being asserted active low
per Figure 31, with the write occurring on the rising edge of
WR.
These work arounds will prevent the occurrence of an
uncontrolled write when CS is asserted low and prevent the
alteration of operational register contents.
Future Revisions
Hardware solutions to correct this undesired write have been
reviewed, and the design may be modified to prevent this
occurrence in future versions of the devices. Any such
changes will be backwards compatible to the existing device,
such that the recommended work-arounds will not affect the
operation of the device in existing designs.
WR_PAD
A0 Z
ALT_WR _A1
RDMODE ^S
WR_TO_CORE
RD_PAD
RDMODE
ALT_RD
A0 Z
A1
S
RD CS_PAD
CS_LATCHED
DQ
GN
FIGURE 29. CS SIMPLIFIED SCHEMATIC
RD
WR
CS
FIGURE 30. READ CYCLE
RD
WR
CS
FIGURE 31. WRITE CYCLE
JTAG Testing
The bi-directional type pins cannot be used as inputs in
EXTEST mode, however they do work in SAMPLE mode.
Work Arounds
The test vectors should be written such that the bi-directional
pins are used only as outputs, with the device on the other
end of the line used as the input. Alternatively, the test
vectors can be written such that SAMPLE mode is used
when treating the bi-directional pins as inputs.
42
FN6004.3
July 8, 2005