ISL5217_05 Datasheet, PDF (38/43 Pages) Intersil Corporation – Quad Programmable Up Converter

ISL5217
Miscellaneous Control Registers
TABLE 44. TEST CONTROL (15:0)
TYPE: SINGLE CHANNEL DIRECT, ADDRESS: 0x17
BIT
FUNCTION
DESCRIPTION
15
FSRX and SCLKX shut off FSRX and SCLKX, from default, turn off synchronously to CLK. Set to 1 to enable FSRX and SCLKX
signals to be shut off on the boundary of SCLKX.
14:13 Serial Transfer Delay
Set both these bits to allow back-to-back serial transfers by programming the delay for the internal
serial data. Setting 0x17, bit 14 delays the internal serial data bit by the serial clock pipeline latency
through the input pad. Setting 0x17, bit 13 delays and aligns the internal sample_clk_32x to match the
FIFO timing so no dead cycles occur.
12
Filter Coefficient mode
Set to 1 to enable 24-bit floating point mode. Default (reset) mode is 16-bit 2’s complement.
0=2’s complement.
1=24-bit floating point.
11
Reserved
Not used.
10
Pad hold adjustment
Hold select for serial data.
9
Pad Hold Adjustment
Hold select for CS and A[6:0].
8
Pad Hold Adjustment
Hold select for d in of IIN[19:0] and QIN[19:0].
7
PN Gen Enable
Turn on PN Generator.
6
PN Gen Rate
When asserted high forces PN gen to run at the clock rate. When asserted low forces PN gen to run
at the symbol rate
5
Reserved
Not used
4
Straight Thru
Pass FIFO output directly to the int filter, (bypasses the shaping filter and FM generator)
3
Select PN Generator
Select PN generator as the source for FIFO data in
2
Force Edge
Bypass sample NCO control and move data in the shaping and interpolation filter every clock
1
Force FIFO En
Bypass sample NCO control and move data from the FIFO every clock.
0
Force Carrier ROM
Force output of SIN/COS ROM, sin=cos= 0x1FFFF.
NOTE: Test controls (10:7) are valid for Channel 0 only. They are not used and cleared to zero in channels 1-3.
BIT
15
14
14:11
10
9:8
FUNCTION
Immediate Update (Top
Cont. Reg Update)
BIST Mode Control
Reserved
Output 2X Select
Output Mode (1:0)
TABLE 45. DEVICE CONTROL
TYPE: DEVICE CONTROL DIRECT, ADDRESS: 0x78
DESCRIPTION
Allows µP writes to bypass the update mask and load the selected top configuration slave register
immediately from the master, (requires 4 CLK synchronization). This update only affects Top Output
Routing Control, 0x79.
Built in Self Test (BIST) mode control pin. Set to 1 to enter the BIST test mode.
0=BIST Disabled (default).
1=BIST mode enabled.
Not used
Used to set the muxed I/Q at 2X rate output mode to output data at twice the sample rate. When enabled
the clock is used to select I data when the clock is high and Q data when the clock is low. This bit is only
used in conjunction with Output mode (1:0) = 01, selecting Four channel I data out at 104MHz, (4 x 20)
when disabled, and Muxed I/Q at the 2X rate when enabled.
0 = Disabled
1 = Enabled
Configures output mode of device.a
00 = I and Q cascade in, (2 x 20), I and Q cascade out, (2 x 20)
01 = Four channel I data out at 104MHz, (4 x 20)
10 = Four channel Q data out at 104MHz, (4 x 20)
11 = Four channel muxed I/Q data out at 52MHz, (4 x 20)
38
FN6004.3
July 8, 2005