ISL5217_05 Datasheet, PDF (27/43 Pages) Intersil Corporation – Quad Programmable Up Converter

ISL5217
BIT
FUNCTION
15:2 Reserved
1
Reset
0
Sync Out
TABLE 14. DEVICE IMMEDIATE ACTION
TYPE: DEVICE CONTROL DIRECT, ADDRESS: 0x7f
DESCRIPTION
Not Used.
Hard Reset. Self clearing pulse zeroes data RAMs, returns master and slave configuration registers to
their default values, etc. The device is in an idle state after reset.
Software Sync Out. Self clearing pulse used to synchronize multiple devices. See Figure 3.
Single Channel Direct Control Registers
TABLE 15. SINGLE CHANNEL DIRECT REGISTER MAP
DIRECT
ADDRESS
(4:0)
TYPE
UPDATE
STROBE
ALWAYS
UPDATE
IMMEDIATE
SLAVE
LOCATION
FUNCTION
00
R/W
X
X
FIFO
I Channel Input or FM <15:0>.
01
R/W
X
FIFO
Q Channel input <15:0>.
02
R/W
Sample NCO Fixed Integer divider <31:16> MSW.
03
R/W
X
Sample NCO Fixed Integer divider <15:0> LSW.
04
R/W
Sample NCO Sample Freq <47:32>, MSW.
05
R/W
Sample NCO Sample Freq <31:16>.
06
R/W
X
Sample NCO Sample Freq <15:0>, LSW.
07
R/W
X
Carrier NCO Carrier Freq static phase offset <15:0>.
08
R/W
Carrier NCO Carrier Freq MSW <15:0>.
09
R/W
X
Carrier NCO Carrier Freq LSW <15:0>.
0a
R/W
X
Final Gain Gain <15:0>.
0b
R/W
X
µP Interface Gain Profile length <8:0>.
0c
R/W
X
µP Interface Main Control <15:0>.
0d
R/W
X
Timing and Cntrl,
Sample NCO,
IQ FIFO, FIR and
Gain
FIR Control <15:0>.
0e
R/W
X
µP Interface Update Mask <15:0>.
0f
W
µP Interface Immediate Action<15:0>.
10
R/W
X
µP Interface Polarity Control<15:0>.
11
R/W
X
Timing and Cntrl, Serial Control <15:0>.
Serial Interface
12
R/W
X
Serial Interface I Serial Time slot<15:0>.
13
R/W
X
Serial Interface Q Serial Time slot<15:0>.
14
W
µP Interface RAM Data <15:0>.
15
W
X
µP Interface RAM Address <15:0>.
16
R
µP Interface Status <15:0>.
17
R/W
X
µP Interface Test Control<15:0>.
18:1F
Not Used.
RESET DEFAULT
-
-
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
0x0000
0x0000
0x0000
27
FN6004.3
July 8, 2005