ISL5217_05 Datasheet, PDF (23/43 Pages) Intersil Corporation – Quad Programmable Up Converter

ISL5217
AC Electrical Specifications V_CCC = 2.5 ± 5%, V_CCIO = 3.3 ± 5%, T_A = -40^oC to 85^oC (Note 6) (Continued)
PARAMETER
SYMBOL
MIN
MAX
UNITS
IIN<19:0> or QIN<19:0> Delay Time from CLK
IOUT<19:0> or QOUT<19:0> Delay Time from CLK
IIN<19:0> or QIN<19:0> Valid Time from CLK, 2X Rate
IOUT<19:0> or QOUT<19:0> Valid Time from CLK, 2X Rate
SCLKX Valid Time from CLK, SCLX = CLK
SCLKX Valid Time from CLK, SCLX = Divided CLK
t _IQIDC
2
7
ns
t _IQODC
2
7
ns
t _IQVC2X
2
8
ns
t _IQVC2X
2
8
ns
t _SVC1X
2
7
ns
t SVC
2
7
ns
ISTRB Delay Time from CLK
t _IDC
2
6
ns
FSRX Delay Time from CLK
t _FDC
-
7
ns
SYNCO Delay Time from CLK
t _SDC
-
9
ns
P<15:0> Delay Time from CLK
t _PDC
-
16
ns
P<15:0> Delay Time from A<6:0> or CS
t _PDAC
-
20
ns
P<15:0> Delay Time from A<6:0> or CS (RDMODE=1)
t _PDAC1
-
20
ns
Output Rise/Fall Time (Note 7)
t _RF
-
3
ns
NOTES:
6. AC tests performed with C_L = 70pF. Input reference level for CLK is 1.5V, all other inputs 1.5V.
Test V_IH = 3.0V, V_IHC = 3.0V, V_IL = 0V, V_OL = 1.5V, V_OH = 1.5V.
7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
AC Test Load Circuit
S₁
DUT
C_L †
SWITCH S₁ OPEN FOR I_CCSB AND I_CCOP
† TEST HEAD CAPACITANCE
±
I_OH
1.5V
I_OL
EQUIVALENT CIRCUIT
Waveforms
t_CLK
t_CH t_CL
t_CLK = 1 / F_CLK
CLK
RESET
t_RHC
t_RPW
t_RSC
FIGURE 19. CLOCK AND RESET TIMING
CLK
t_SVC
SCLKX
t_FDC
FSRX
SDX
t_SSS
t_SHS
FIGURE 20. SERIAL INTERFACE RELATIVE TIMING
23
FN6004.3
July 8, 2005