ISL5217_05 Datasheet, PDF (2/43 Pages) Intersil Corporation – Quad Programmable Up Converter

Functional Block Diagram
ISL5217
SDA
SDB
SDC
SDD
CLK
A<6:0>
P<15:0>
TXENA
TXENB
TXENC
TXEND
UPDA
UPDB
UPDC
UPDD
WR
RD
CS
RESET
RDMODE
OUTEN<1:0>
TRITST
OFFBIN
TMS
TDI
TCK
TRST
SERIAL
INTERFACE
I IN<15:0>
Q IN<15:0>
I IN<15:0>
Q IN<15:0>
SER._PAR.
CHANNEL
UP
INTERFACE
AND TIMING
FM
I FM 18
/
MOD.
Q FM ¹⁸
/
20
I SF 20
/
/
20
/
/ ₁₆
I FIFO
Q FIFO/
/
16
/
SHAPING
FILTER
MOD. TYPE <1:0>
FID<31:0>
SR<47:0>
INTPL PHASES<1:0>
PHASE OFFSET<1:0>
SAMPLE
NCO
GAIN<11:0>
GAIN PROFILE LENGTH<6:0>
COARSE
PHASE<3:0>
OUTPUT_EN
CARRIER PHASE<15:0>
CARRIER FREQUENCY<31:0>
DUALQUADMODE (CH0 AND CH2 ONLY)
DEVICE
UPROCESSOR
INTERFACE
ISTROBEUPDATE
RESET
CASCADE_DELAY<1:0>
ROUTEBUS<15:0>
CASCADE_IN_ENABLE
OUTPUTMODE<1:0>
OUTPUTMODE2X
I_STROBE_EN
ISTROBEPOLARITY
TRITST_ENABLE_BUS<7:0>
HALF
BAND
BYPASS
CH_ENABLE<0>
21
/ _COMPLEX
21
/ ^MIXER
FINE
PHASE<11:0>
I<21:0>
Q<21:0>
4 INPUT
SUMMER
1
ROUTING
CONTROL
CARRIER
NCO
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
I<21:0>
Q<21:0>
CH_EN<1>
I<21:0>
Q<21:0>
CH_EN<2>
I<21:0>
Q<21:0>
CH_EN<3>
4 INPUT
SUMMER
2
4 INPUT
SUMMER
3
4 INPUT
SUMMER
4
OUTPUT
CONTROL
JTAG
SCLKA
FSRA
SCLKB
FSRB
SCLKC
FSRC
SCLKD
FSRD
ISTRB
IOUT<19:0>
QOUT<19:0>
IIN<19:0>
QIN<19:0>
SYNCO
TDO