ISL5217_05 Datasheet, PDF (20/43 Pages) Intersil Corporation – Quad Programmable Up Converter

ISL5217
6. Software TXENX Assertion - Upon assertion of a channel
software TXENX (bit 0 of cword 0x0c), the enabled slave
registers are updated.
Starting Sequence
Channel processing begins when the slave register of the
sample frequency and the interpolation phase are updated
with a non-zero value. The sample rate NCO provides the
timing strobes that drive the channel processing logic.
The starting sequence can be applied to one channel,
multiple channels, and multiple devices.
When starting multiple channels through a software update,
a broadcast write, to an immediate action register in the
channel address space asserts an update strobe.
When starting multiple QPUCs through a software update, a
write to the top control immediate action register, 0x78, bit 15
asserts the SYNCO pin. The first chip acts as a master and
is tied to an UPDX pin of the remaining chips.
A delayed starting sequence of a channel can be realized by
taking advantage of the On line mode defined in Main control
(0xc, bit 6). The On line mode allows µP access to the
RAM’s and allows the NCO’s to operate normally but inhibits
processing by forcing the FIFO data to zero.
JTAG and Built in Self Test
JTAG: The IEEE 1149.1 Joint Test Action Group boundary
scan standard operational codes shown in Table 9 are
supported. A separate application note is available with
implementation details and the BSDL file is available.
TABLE 9. JTAG OP CODES SUPPORTED
INSTRUCTION
OP CODE
EXTEST
0000
IDCODE
0001
SAMPLE/PRELOAD
0010
INTEST
0011
BYPASS
1111
not at specified levels. During the power-up and power-down
operations, differences in the starting point and ramp rates of
the two supplies may cause current to flow in the isolation
structures which, when prolonged and excessive, can
reduce the usable life of the device. In general, the most
preferred case would be to power-up or down the core and
I/O structures simultaneously. However, it is also safe to
power-up the core prior to the I/O block if simultaneous
application of the supplies is not possible. In this case, the
I/O voltage should be applied within 10 ms to 100 ms
nominally to preserve component reliability. Bringing the
core and I/O supplies to their respective regulation levels in a
maximum time frame of a 100 ms, moderates the stresses
placed on both the power supply and the ISL5217. When
powering down, simultaneous removal is preferred, but It is
also safe to remove the I/O supply prior to the core supply. If
the core power is removed first, the I/O supply should also
be removed within 10-100mS.
Self test is initiated by resetting the part and then loading a
given configuration register set, filter coefficient set, and gain
profile ramp. Control word 0x78, bit 14 should be set to 1 to
enter the self test mode. Upon assertion of a channel 0
update anded with updateMask bit 15, the device will begin
computing a signature which may then be read back from
control word 0x7d, bits <14:3>. Control word 0x7d, bit 15
reflects the validity (completion) of the test. This bit will be
cleared upon assertion of the 0x78, bit 14 test mode bit or
upon assertion of the channel 0 update and will be set to 1
upon completion of the test.
Power-up Sequencing
The ISL5217 core and I/O blocks are isolated by structures
which may become forward biased if the supply voltages are
20
FN6004.3
July 8, 2005