ISL6336D Datasheet, PDF (4/30 Pages) Intersil Corporation – VR11.1, 6-Phase PWM Controller with Phase Dropping,Droop Disabled and Load Current Monitoring Features

Pin Configuration
ISL6336D
ISL6336D
(48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
VID7 1
36 PWM3
VID6 2
35 ISEN3-
VID5 3
VID4 4
VID3 5
VID2 6
VID1 7
VID0 8
PSI# 9
OFS 10
IMON 11
DAC 12
GND
34 ISEN3+
33 ISEN1+
32 ISEN1-
31 PWM1
30 PWM4
29 _ISEN4-
28 _ISEN4+
27 _ISEN2+
26 _ISEN2-
25 _PWM2
13 14 15 16 17 18 19 20 21 22 23 24
Pin Descriptions
PIN #
PIN NAME
DESCRIPTION
1, 2, 3, 4,
5, 6, 7, 8
VID7, VID6, VID5, VID4, These are the inputs to the internal DAC that generate the reference voltage for output regulation. All VID pins
VID3, VID2, VID1, VID0 have no internal pull-up current sources until after TD3. Connect these pins either to open-drain outputs with
external pull-up resistors or to active pull-up outputs, as high as VCC plus 0.3V.
9
PSI#
A low input signal indicates the low power mode operation of the processor. The controller drops the number of
active phases to single or 2-phase operation, according to the logic on Table 2 on page 14. The PSI# pin, SS, and
FS pins are used to program the controller in operation of noncoupled, 2-Phase coupled, or (n-x)-Phase coupled
inductors when PSI# is asserted (active low). Different cases yield different PWM output behavior on both
dropped phase(s) and remaining phase(s) as PSI# is asserted and deasserted. A high input signal pulls the
controller back to normal operation.
10
OFS
The OFS pin can be used to program a DC offset current, which will generate a DC offset voltage between the
REF and DAC pins. The offset current is generated via an external resistor and precision internal voltage
references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no offset, the OFS
pin should be left unterminated.
11
IMON
IMON is the output pin of sensed, thermally compensated (if internal thermal compensation is used) average
current. The voltage at IMON pin is proportional to the load current and the resistor value, and internally clamped
to 1.11V plus the remote ground potential difference. If the clamped voltage (1.11V) is triggered, it will initiate the
overcurrent shutdown. By choosing the proper value for the resistor at IMON pin, the overcurrent trip level can be
set to be lower than the fixed internal overcurrent threshold. During the dynamic VID, the OCP function of this pin
is disabled to avoid false triggering. Tie it to GND if not used.
12, 13
DAC, REF
The DAC pin is the output of the precision internal DAC reference. The REF pin is the positive input of the Error
Amplifier. In typical applications, a 1kΩ, 1% resistor is used between DAC and REF to generate a precision offset
voltage. This voltage is proportional to the offset current determined by the offset resistor from OFS to ground
or VCC. A capacitor is used between REF and ground to smooth the voltage transition during Dynamic VID™
operations.
14
APA
The APA pin is used to adjust the Adaptive Phase Alignment trip level. A 50µA current source flows into this pin. A
resistor connected from this pin to COMP sets the voltage trip level. A small decoupling capacitor should be placed
in parallel with the resistor for high frequency decoupling.
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4
FN8320.0
October 6, 2014