ISL6336D Datasheet, PDF (14/30 Pages) Intersil Corporation – VR11.1, 6-Phase PWM Controller with Phase Dropping,Droop Disabled and Load Current Monitoring Features

ISL6336D
PWM Modulation Scheme
The ISL6336D adopts Intersil's proprietary Active Pulse
Positioning (APP) modulation scheme to improve transient
performance. APP control is a unique dual-edge PWM
modulation scheme with both PWM leading and trailing edges
being independently moved to give the best response to transient
loads. The PWM frequency, however, is constant and set by the
external resistor between the FS pin and GND. To further improve
the transient response, the ISL6336D also implements Intersil's
proprietary Adaptive Phase Alignment (APA) technique. APA,
with sufficiently large load step currents, can turn on all phases
together. With both APP and APA control, ISL6336D can achieve
excellent transient performance and reduce demand on the
output capacitors.
Under steady state conditions, the operation of the ISL6336D
PWM modulators appear to be that of a conventional trailing
edge modulator. Conventional analysis and design methods can
therefore be used for steady state and small signal operation.
PWM and PSI# Operation
The timing of each channel is set by the number of active
channels. The default channel setting for the ISL6336D is four.
The switching cycle is defined as the time between PWM pulse
termination signals of each channel. The cycle time of the pulse
signal is the inverse of the switching frequency set by the resistor
between the FS pin and ground. The PWM signals command the
MOSFET driver to turn on/off the channel MOSFETs.
For the default 6-channel operation, the channel firing order is
1-2-3-4-5-6. The PWM2 pulse happens 1/6 of a cycle after
PWM1, the PWM3 pulse happens 1/6 of a cycle after PWM2,
etc. In PSI# low power mode, the remaining active phase(s) is 1
and/or 4.
For 5-channel operation (PWM6 = 5V), the channel firing order is
1-2-3-4-5. In PSI# low power mode, the remaining active phase(s)
is 1 and/or 3. For 4-channel operation (PWM5 = 5V), the channel
firing order is 1-2-3-4. In PSI# low power mode, the remaining
active phase(s) is 1 and/or 3.
Connecting PWM4 to VCC selects three channel operation and
the pulse times are spaced in 1/3 cycle increments. In PSI# low
power mode, the remaining active phase(s) is 1 and/or 2. If
PWM3 is connected to VCC, two channel operation is selected
and the PWM2 pulse happens 1/2 of a cycle after PWM1 pulse.
In PSI# low power mode, the remaining active phase(s) is 1
and/or 2. If PWM2 is connected to VCC, only Channel 1 operation
is selected.
When PSI# is asserted low, indicating the low power mode
operation of the processor, the controller drops the number of
active phases according to the logic on Table 2 for high light-load
efficiency performance. SS and FS pins are used to program the
controller in operation of noncoupled, 2-phase coupled, or
(n-x)-Phase coupled inductors. Different cases yield different
PWM output behaviors on both dropped phase(s) and remaining
phase(s) as PSI# is asserted and deasserted. A high PSI# input
signal pulls the controller back to normal CCM PWM operation to
sustain an immediate heavy transient load and high efficiency.
Note that “n-x” means n-x phase coupled and x-phase(s) are
uncoupled.
TABLE 2. PSI# OPERATION DECODING
PSI# FS SS
Non CI or (n-1) CI Drops to 1-phase
0
0
0
Non CI or (n-2) CI Drops to 2-phase
0
0
1
2-phase CI Drops to 1-phase
0
1
0
2-phase CI Drops to 2-phase
0
1
1
Normal CCM PWM Mode
1
x
x
While the controller is operational (VCC above POR, EN_VTT and
EN_PWR are both high, valid VID inputs), it can pull the PWM pins
to ~40% of VCC (~2V for 5V VCC bias) during various stages, such
as soft-start delay, phase shedding operation, or fault conditions
(OC or OV events). The matching driver's internal PWM resistor
divider can further raise the PWM potential, but not lower it
below the level set by the controller IC. Therefore, the controller's
PWM outputs are directly compatible with Intersil drivers that
require 5V PWM signal amplitudes. Drivers requiring 3.3V PWM
signal amplitudes are generally incompatible.
Switching Frequency
Switching frequency is determined by the selection of the
frequency-setting resistor, R_T, which is connected from FS pin to
GND or VCC. Equation 3 and Figure 3 are provided to assist in
selecting the correct resistor value.
R_T
=
2----.--5---X-----1---0----¹_---⁰_-
f_SW
(EQ. 3)
where f_SW is the switching frequency of each phase.
250
200
150
100
50
0
100k 200k 300k 400k 500k 600k 700k 800k 900k 1M
SWITCHING FREQUENCY (Hz)
FIGURE 3. SWITCHING FREQUENCY vs RT
Current Sensing
The ISL6336D senses current continuously for fast response. The
ISL6336D supports inductor DCR sensing, or resistive sensing
techniques. The associated channel current sense amplifier uses
the ISEN inputs to reproduce a signal proportional to the inductor
current, I_L. The sense current, I_SEN, is proportional to the inductor
current. The sensed current is used for current balance and
overcurrent protection.
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October 6, 2014