ISL6336D Datasheet, PDF (16/30 Pages) Intersil Corporation – VR11.1, 6-Phase PWM Controller with Phase Dropping,Droop Disabled and Load Current Monitoring Features

ISL6336D
The voltage on the capacitor V_C, can be shown to be proportional
to the channel current I_L. See Equation 8.
V_Cs
=
-^--^s-----^---^R----E-----S----^S----^E-----^L---N--------+-----¹---^----^---^---^R----^S----^E----^N-----^---^I--^L----^
s  RC + 1
(EQ. 8)
If the R-C network components are selected such that the RC
time constant matches the ESL-RSEN time constant (R*C =
ESL/R_SEN), the voltage across the capacitor V_C is equal to the
voltage drop across the R_SEN, i.e., proportional to the channel
current. As an example, a typical 1mΩ sense resistor can use
R = 348 and C = 820pF for the matching. Figures 6 and 7 show
the sensed waveforms without and with matching RC when using
resistive sense.
Because of the internal filter at the ISENn- pin, one capacitor, C_T,
is needed to match the time delay between the ISENn- and
ISENn+ signals. Select the proper C_T to keep the time constant of
R_ISEN and C_T (R_ISEN x C_T) close to 27ns.
on current sensing will not provide a fast OCP response and hurt
system reliability.
LOAD
V_IMON
FIGURE 8. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
LOAD
V_IMON
FIGURE 9. LOAD TRANSIENT RESPONSE WHEN R-C TIME
CONSTANT IS TOO SMALL
FIGURE 6. VOLTAGE ACROSS R WITHOUT RC
LOAD
V_IMON
FIGURE 7. VOLTAGE ACROSS C WITH MATCHING RC
Equation 9 shows that the ratio of the channel current to the
sensed current, I_SEN, is driven by the value of the sense resistor
and the R_ISEN.
I_SEN
=
I_L

-^R-----^S----^E----^N---
R_ISEN
(EQ. 9)
L/DCR OR ESL/R_SEN MATCHING
Assuming the compensator design is correct, Figure 8 shows the
expected load transient response waveforms if L/DCR or
ESL/R_SEN is matching the R-C time constant. When the load
current has a square change, the IMON voltage (VIMON) without
a decoupling capacitor also has a square response. However,
there is always some PCB contact impedance of current sensing
components between the two current sensing points; it hardly
accounts into the L/DCR or ESL/R_SEN matching calculation. Fine
tuning the matching is necessarily done in the board level to
improve overall transient performance and system reliability.
If the R-C timing constant is too large or too small, V_C(s) will not
accurately represent real-time I_OUT(s) and will worsen fault
response at the transient event. Figure 9 shows the IMON
transient voltage response when the R-C timing constant is too
small. V_IMON will sag excessively upon load insertion and may
create a system failure or early overcurrent trip. Figure 10 shows
the transient response when the R-C timing constant is too large.
V_IMON is sluggish in reaching its final value. The excessive delay
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FIGURE 10. LOAD TRANSIENT RESPONSE WHEN R-C TIME
CONSTANT IS TOO LARGE
Channel-Current Balance
The sensed current I_n from each active channel is summed
together and divided by the number of active channels. The
resulting average current I_AVG provides a measure of the total
load current. Channel current balance is achieved by comparing
the sensed current of each channel to the average current to
make an appropriate adjustment to the PWM duty cycle of each
channel with Intersil’s patented current-balance method.
Channel current balance is essential in achieving the thermal
advantage of multiphase operation. With good current balance,
the power loss is equally dissipated over multiple devices and a
greater area.
Voltage Regulation
The compensation network shown in Figure 11 assures that the
steady-state error in the output voltage is limited only to the error
in the reference voltage (output of the DAC) and offset errors in
the OFS current source, remote-sense and error amplifiers.
Intersil specifies the guaranteed tolerance of the ISL6336D to
include the combined tolerances of each of these elements.
The output of the error amplifier, V_COMP, is compared to
sawtooth waveforms to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference voltage.
The internal and external circuitry, which control voltage
regulation, are illustrated in Figure 11.
FN8320.0
October 6, 2014