ISL6336D Datasheet, PDF (27/30 Pages) Intersil Corporation – VR11.1, 6-Phase PWM Controller with Phase Dropping,Droop Disabled and Load Current Monitoring Features

ISL6336D
Output Filter Design
The output inductors and the output capacitor bank together to
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must provide
the transient energy until the regulator can respond. Because it
has a low bandwidth compared to the switching frequency, the
output filter necessarily limits the system transient response. The
output capacitor must supply or sink load current while the
current in the output inductors increases or decreases to meet
the demand.
In high-speed converters, the output capacitor bank is usually the
most costly (and often the largest) part of the circuit. Output filter
design begins with minimizing the cost of this part of the circuit.
The critical load parameters in choosing the output capacitors are
the maximum size of the load step, I; the load-current slew rate,
di/dt; and the maximum allowable output-voltage deviation under
transient loading, V_MAX. Capacitors are characterized according
to their capacitance, ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors supply
all of the transient current. The output voltage will initially deviate by
an amount approximated by the voltage drop across the ESL. As the
load current increases, the voltage drop across the ESR increases
linearly until the load current reaches its final value. The capacitors
selected must have sufficiently low ESL and ESR so that the total
output-voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount, as
shown in Equation 32:
V  ESL -d---i + ESR I
dt
(EQ. 32)
The filter capacitor must have sufficiently low ESL and ESR so
that V < V_MAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination with
bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the bulk
capacitors allows them to supply the increased current with less
output voltage deviation.
The ESR of the bulk capacitors also creates the majority of the
output-voltage ripple. As the bulk capacitors sink and source the
inductor AC ripple current (see “Interleaving” on page 13 and
Equation 2), a voltage develops across the bulk-capacitor ESR
equal to I_C,PP (ESR). Thus, once the output capacitors are
selected, the maximum allowable ripple voltage, V_P-P(MAX),
determines the lower limit on the inductance, as shown in
Equation 33.
L  ESR -^--V-----^I-^N------^–----N------V----^O----^U----^T----^----V----^O----^U----^T--
f_{S W} V_{I N} V_{P-P M A X }
(EQ. 33)
Since the capacitors are supplying a decreasing portion of the
load current while the regulator recovers from the transient, the
capacitor voltage becomes slightly depleted. The output
inductors must be capable of assuming the entire load current
before the output voltage decreases more than V_MAX. This
places an upper limit on inductance.
Equation 34 gives the upper limit on L for the cases when the
trailing edge of the current transient causes a greater output-
voltage deviation than the leading edge. Equation 35 addresses
the leading edge. Normally, the trailing edge dictates the
selection of L because duty cycles are usually less than 50%.
Nevertheless, both inequalities should be evaluated, and L
should be selected based on the lower of the two results. In each
equation, L is the per-channel inductance, C is the total output
capacitance, and N is the number of active channels.
L  -2---N-----C-----V---^O----
I²
V_MAX – IESR
(EQ. 34)
L  -^--1---.--2---5----^--N-----C---
I²
V_MAX – IESR
^{VIN – VO}
(EQ. 35)
Switching Frequency Selection
There are a number of variables to consider when choosing the
switching frequency, as there are considerable effects on the
upper MOSFET loss calculation. These effects are outlined in
“MOSFETs” on page 25, and they establish the upper limit for the
switching frequency. The lower limit is established by the
requirement for fast transient response and small output-voltage
ripple as outlined in “Output Filter Design” on page 27. Choose
the lowest switching frequency that allows the regulator to meet
the transient-response requirements.
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper MOSFETs.
Their RMS current capacity must be sufficient to handle the AC
component of the current drawn by the upper MOSFETs, which is
related to duty cycle and the number of active phases.
For a 2-phase design, use Figure 23 to determine the input
capacitor RMS current requirement given the duty cycle,
maximum sustained output current (I_O), and the ratio of the
per-phase peak-to-peak inductor current (I_L(P-P)) to I_O. Select a
bulk capacitor with a ripple current rating which will minimize the
total number of input capacitors required to support the RMS
current calculated. The voltage rating of the capacitors should
also be at least 1.25x greater than the maximum input voltage.
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FN8320.0
October 6, 2014