ISL6336D Datasheet, PDF (29/30 Pages) Intersil Corporation – VR11.1, 6-Phase PWM Controller with Phase Dropping,Droop Disabled and Load Current Monitoring Features

ISL6336D
Next, place the input and output capacitors. Position one high
frequency ceramic input capacitor next to each upper MOSFET
drain. Place the bulk input capacitors as close to the upper
MOSFET drains, as dictated by the component size and
dimensions. Long distances between input capacitors and
MOSFET drains result in too much trace inductance and a
reduction in capacitor performance. Locate the output capacitors
between the inductors and the load, while keeping them in close
proximity to the microprocessor socket.
Voltage-Regulator (VR) Design
Materials
Intersil has also developed a set of worksheets to support VR
design and layout. Contact Intersil’s local office or field support
for the latest available information.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
October 6, 2014
FN8320.0 Initial Release
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FN8320.0
October 6, 2014