ISL54100_14 Datasheet, PDF (4/21 Pages) Intersil Corporation – TMDS Regenerators with Multiplexers

ISL54100, ISL54101, ISL54102
Electrical Specifications Specifications apply for V_D = 3.3V, pixel rate = 165MHz, T_A = +25°C, RES_TERM = 1kΩ, RES_BIAS = 3.16kΩ,
TMDS output load = 50Ω, TMDS output termination voltage V_TERM = 3.0V unless otherwise noted.
SYMBOL
PARAMETER
COMMENT
MIN
(Note 2)
TYP
MAX
(Note 2)
UNIT
DIGITAL OUTPUT CHARACTERISTICS
V_OH
Output HIGH Voltage, I_O = 8mA
V_OL
Output LOW Voltage, I_O = -8mA
POWER SUPPLY REQUIREMENTS
2.4
V
0.4
V
V_D
Supply Voltage
I_D
Supply Current
ISL54100
ISL54101
All available inputs driven by
165Mpixel/s TMDS signals.
Default register settings
3
3.3
3.6
V
387
435
mA
357
405
mA
ISL54102
370
415
mA
I_D
Supply Current in Power-down Mode
All available inputs driven by
165Mpixel/s TMDS signals.
20
26
mA
AC TIMING CHARACTERISTICS (2-WIRE INTERFACE)
f_SCL
t_AA
t_BUF
SCL Clock Frequency
SCL LOW to SDA Data Out Valid
Time the Bus Must be Free Before a New
Transmission Can Start
0
400
kHz
200
470
ns
1.3
µs
t_LOW
Clock LOW Time
1.3
0.1
µs
t_HIGH Clock HIGH Time
0.6
0.2
µs
t_SU:STA Start Condition Setup Time
0.6
0.03
µs
t_HD:STA Start Condition Hold Time
0.6
0.07
µs
t_SU:DAT Data In Setup Time
100
0.03
ns
t_HD:DAT Data In Hold Time
0
ns
t_SU:STO Stop Condition Setup Time
0.6
µs
t_DH
Data Output Hold Time
160
ns
NOTE:
2. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
3. Operation up to 165MHz is guaranteed. While many parts will typically operate up to 225MHz, operation above 165MHz is not guaranteed.
SCL
t_SU:STA
SDA IN
SDA OUT
t_F
t_HIGH
t_SU:DAT
t_HD:STA
t_LOW
t_HD:DAT
t_R
t_AA t_DH
FIGURE 1. 2-WIRE INTERFACE TIMING
t_SU:STO
t_BUF
4
FN6275.5
June 4, 2008