ISL54100_14 Datasheet, PDF (18/21 Pages) Intersil Corporation – TMDS Regenerators with Multiplexers

ISL54100, ISL54101, ISL54102
ISL5410x Serial Communication
Overview
The ISL5410x uses a 2-wire serial bus for communication
with its host. SCL is the Serial Clock line, driven by the host
and SDA is the Serial Data line, which can be driven by all
devices on the bus. SDA is open drain to allow multiple
devices to share the same bus simultaneously.
Communication is accomplished in three steps:
1. The Host selects the ISL5410x it wishes to communicate
with.
2. The Host writes the initial ISL5410x Configuration
Register address it wishes to write to or read from.
3. The Host writes to or reads from the ISL5410x’s
Configuration Register. The ISL5410x’s internal address
pointer auto increments, so to read registers 0x00
through 0x1B, for example, one would write 0x00 in step
2, then repeat step three 28 times, with each read
returning the next register value.
The ISL5410x has a 7-bit address on the serial bus,
determined by the ADDR0-ADDR6 bits. This allows up to
128 ISL5410xs to be independently controlled by the same
serial bus.
The bus is nominally inactive, with SDA and SCL high.
Communication begins when the host issues a START
command by taking SDA low while SCL is high (Figure 14).
The ISL5410x continuously monitors the SDA and SCL lines
for the start condition and will not respond to any command
until this condition has been met. The host then transmits the
7-bit serial address plus a R/W bit, indicating if the next
transaction will be a Read (R/W = 1) or a Write (R/W = 0). If
the address transmitted matches that of any device on the
bus, that device must respond with an ACKNOWLEDGE
(Figure 15).
Once the serial address has been transmitted and
acknowledged, one or more bytes of information can be
written to or read from the slave. Communication with the
selected device in the selected direction (read or write) is
ended by a STOP command, where SDA rises while SCL is
high (Figure 14), or a second START command, which is
commonly used to reverse data direction without
relinquishing the bus.
Data on the serial bus must be valid for the entire time SCL
is high (Figure 16). To achieve this, data being written to the
ISL5410x is latched on a delayed version of the rising edge
of SCL. SCL is delayed and deglitched inside the ISL5410x
for three crystal clock periods (120ns for a 25MHz crystal) to
eliminate spurious clock pulses that could disrupt serial
communication.
When the contents of the ISL5410x are being read, the SDA
line is updated after the falling edge of SCL, delayed and
deglitched in the same manner.
Configuration Register Write
Figure 17 shows two views of the steps necessary to write
one or more words to the Configuration Register.
Configuration Register Read
Figure 18 shows two views of the steps necessary to read
one or more words from the Configuration Register.
SCL
SDA
START
STOP
FIGURE 14. VALID START AND STOP CONDITIONS
SCL FROM
HOST
1
DATA OUTPUT
FROM TRANSMITTER
8
9
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 15. ACKNOWLEDGE RESPONSE FROM RECEIVER
18
FN6275.5
June 4, 2008