ISL54100_14 Datasheet, PDF (12/21 Pages) Intersil Corporation – TMDS Regenerators with Multiplexers

ISL54100, ISL54101, ISL54102
Register Listing (Continued)
ADDRESS REGISTER (DEFAULT VALUE) BIT(S) FUNCTION NAME
DESCRIPTION
0x07
Equalization 1 (0xCC)
3:0 Channel A Equalizer Boost (dB) = 1dB + <gain value> * 0.8dB
Gain
0x0: 1dB boost at 800MHz
7:4 Channel B Equalizer _{0xC: 10.6dB boost at 800MHz (default)}
Gain
0xF: 13dB boost at 800MHz
0x08
Equalization 2 (0xCC)
3:0 Channel C Equalizer Boost (dB) = 1dB + <gain value> * 0.8dB
Gain
0x0: 1dB boost at 800MHz
7:4 Channel D Equalizer _{0xC: 10.6dB boost at 800MHz (default)}
Gain
0xF: 13dB boost at 800MHz
0x09
Test Pattern Generator (0x00)
1:0 Generator Mode
When a 25MHz to 165MHz clock is applied to the selected
channel’s clock input, this function will output a PRBS7
pattern on the TX pins.
0: Normal operation (test patterns disabled)
1: PRBS7 pattern
2: Low frequency toggle (0000011111…)
3: High frequency toggle (1010101010…)
Note: When switching from the high frequency toggle
pattern to the low frequency toggle pattern, you must first
select normal operation.
2 Enable PRBS7 Error Enables PRBS7 error counter in registers 0x0A to 0x0C.
Counter
0: Disable PRBS7 Error Counter
1: Enable PRBS7 Error Counter
0x0A
PRBS7 Error Counter Link 0 (read only) 7:0 PRBS7 Error
Counter Link 0
PRBS7 Error Counter of Link 0. Saturates at 0xFF. Reading
this register clears this register at end of read
0x0B
PRBS7 Error Counter Link 1 (read only) 7:0 PRBS7 Error
Counter Link 1
PRBS7 Error Counter of Link 1. Saturates at 0xFF. Reading
this register clears this register at end of read
0x0C
PRBS7 Error Counter Link 2 (read only) 7:0 PRBS7 Error
Counter Link 2
PRBS7 Error Counter of Link 2. Saturates at 0xFF. Reading
this register clears this register at end of read
0x10
PLL Bandwidth (0x10)
Recommended default: 0x12
1:0 PLL Bandwidth
Selects between 4 PLL bandwidth settings
0: 4MHz (silicon default)
1: 2MHz
2: 1MHz (recommended default)
3: 500kHz
1MHz provides slightly better performance with high jitter/
high noise signals.
7:2 Reserved
Keep set to 000100 binary.
12
FN6275.5
June 4, 2008