ISL54100_14 Datasheet, PDF (11/21 Pages) Intersil Corporation – TMDS Regenerators with Multiplexers

ISL54100, ISL54101, ISL54102
Register Listing (Continued)
ADDRESS REGISTER (DEFAULT VALUE)
0x04
Termination Control (0x00)
0x05
Output Options (0x00)
0x06
Data Output Drive (0x00)
BIT(S) FUNCTION NAME
DESCRIPTION
0 Data Termination A 0: Channel A TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel A TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
1 Data Termination B 0: Channel B TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel B TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
2 Data Termination C 0: Channel C TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel C TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
3 Data Termination D 0: Channel D TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel D TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
4 Clk Termination A 0: Channel A TMDS Clock inputs terminated into 50Ω
(normal operation)
1: Channel A TMDS Clock inputs terminated into 100Ω (for
paralleled inputs)
5 Clk Termination B 0: Channel B TMDS Clock inputs terminated into 50Ω
(normal operation)
1: Channel B TMDS Clock inputs terminated into 100Ω (for
paralleled inputs)
6 Clk Termination C 0: Channel C TMDS Clock inputs terminated into 50Ω
(normal operation)
1: Channel C TMDS Clock inputs terminated into 100Ω (for
paralleled inputs)
7 Clk Termination D 0: Channel D TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel D TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
0 Tri-state Clock
Outputs
0: Normal Operation
1: Clock outputs tri-stated (allows another chip to drive the
output clock pins)
1 Tri-state Data
Outputs
0: Normal Operation
1: Data outputs tri-stated (allows another chip to drive the
output data pins)
2 Invert Output
Polarity
0: Normal Operation
1: The polarity of the TMDS data outputs is inverted
(+ becomes -, - becomes +). TMDS clock unchanged.
3 Reverse Output
Order
0: Normal Operation
1: CH0 data is output on CH2 and CH2 data is output on
CH0. No change to CH1.
3:0 Transmit Current
Transmit Drive Current for data signals, adjustable in
0.125mA steps. Clock current is fixed at 10mA.
0x0: 10mA
0x8: 11mA
0xF: 11.875mA
7:4 Transmit
Pre-emphasis
Drive boost (in 0.125mA steps) added during first half of
each bit period for data signals. Clock signals do not have
pre-emphasis.
0x0: 0mA
0x8: 1mA
0xF: 1.875mA
11
FN6275.5
June 4, 2008