ISL54100_14 Datasheet, PDF (13/21 Pages) Intersil Corporation – TMDS Regenerators with Multiplexers

ISL54100, ISL54101, ISL54102
Application Information
The ISL54100, ISL54101, and ISL54102 are TMDS
regenerators, locking to the incoming DVI or HDMI signal
with triple Clock Data Recovery units (CDRs) and a Phase
Locked Loop (PLL). The PLL generates a low jitter pixel
clock from the incoming TMDS clock. The TMDS data
signals are equalized, sliced by the CDR, re-aligned to the
PLL clock, and sent out the TMDS outputs. The ISL54100
and ISL54102 also include an input multiplexer.
Multiplexer Operation
The ISL54100 and ISL54102 have 4:1 and 2:1 (respectively)
input multiplexers. After power-up or a hardware reset, the
IC defaults to hardware channel selection, using the
AUTO_CH_SEL and CH_SEL_x pins. If AUTO_CH_SEL is
pulled high, the highest priority channel with an active TMDS
clock will be automatically selected (Channel A = highest
priority, B = second highest priority, C = second lowest, and
D = lowest priority). If, for example, a DVD player is attached
to Channel A, a set-top-box (STB) is attached to Channel B,
and a video game is attached to Channel C, the DVD player
will have the highest priority, overriding the STB and the
video game whenever the DVD player is transmitting a
TMDS clock. Likewise, the STB will have higher priority than
the video game. Table 1 shows the auto channel selection
priority matrix.
TABLE 1. AUTO CHANNEL SELECTION PRIORITIES
(ISL54102 OPTIONS IN BLUE)
CHANNEL A CHANNEL B CHANNEL C CHANNEL D OUTPUT
Inactive
Inactive
Inactive
Inactive Inactive
Active
Don’t Care Don’t Care Don’t Care Channel A
Inactive
Active
Don’t Care Don’t Care Channel B
Inactive
Inactive
Active
Don’t Care Channel C
Inactive
Inactive
Inactive
Active Channel D
In the auto channel select mode, the CH_SEL_x pins are
outputs indicating the selected channels. Note that in the
Power-down mode, the state of the CH_SEL_x pins is
undetermined/random.
If manual channel selection is desired, the AUTO_CH_SEL
pin should be tied to ground, and the CH_SEL_x pins are
inputs, selecting the desired channel.
The input multiplexer can also be controlled by software via
the I²C interface. Software control is initiated by writing a 0 to
the Hardware Channel Select bit (bit 3 of register 0x02). In
this case, the Auto Channel Select bit (bit 2 of register 0x02)
and the Channel Select bits (bits 0 and 1 of register 0x02)
perform the same functions as the external pins described
above. In the Auto Channel Select mode, the Channel
Select bits are read only, indicating the currently selected
channel. In the Manual Channel Select mode, the Channel
Select bits are read/write, and used to select the channel.
Activity Detection
A channel is considered active using one of two methods. The
original default activity detect method (register 0x03b4 = 1) is
to measure the common mode of the TMDS clock input for
each channel. If the common mode is 3.3V, it indicates that
there is nothing connected to that input, or that whatever is
connected is turned off (inactive). This has been found to be
relatively unreliable, particularly with weak signals.
The preferred method of activity detection is looking for an
active AC signal on the TMDS clock input for that channel
(register 0x03b4 = 1). This is more robust, however
disconnected inputs will cause both inputs to the differential
receiver to be the same level - 3.3V. If the offset error of the
differential TMDS receiver is very small, the receiver can not
resolve a 1 or a 0 and will randomly switch between states,
which may be detected as an active clock. Register 0x03 bits
5 and 6 allow a 10mV or 20mV offset to be added to the input
stage of the clock inputs, eliminating this problem. This offset
will slightly reduce the sensitivity of TMDS receiver for the
clock lines, but since the clock signals are much lower
frequency than the data, they will not be nearly as
attenuated, so this is not a problem in practice.
Again, using the AC activity detection method (register
0x03b4 = 0) is recommended.
Rx Equalization
Registers 0x07 and 0x08 control the amount of equalization
applied to the TMDS inputs, with 4 bits of control for each
channel. The equalization range available is from a minimum
of 1dB boost to a maximum of 13dB at 800MHz, in 0.8dB
increments. Ideally, the equalization is adjusted in the final
application to provide optimal performance with the specific
DVI/HDMI transmitter and cable used. In general, the
amount of equalization required is proportional to the cable
length. If the equalization must be fixed (can not be adjusted
in the final application), an equalization setting of 0xA works
well with short cables as well as medium to longer cables.
Tx Pre-emphasis
The transmit pre-emphasis function sinks additional current
during the first bit after every transition, increasing the slew
rate for a given capacitance, and helping to maintain the
slew rate when using longer/higher capacitance cables.
Pre-emphasis is controlled by register 0x06 bits 7:4, and
ranges from a minimum of 0mA (no pre-emphasis) to
1.875mA (max pre-emphasis).
PLL Bandwidth
The 2-bit PLL Bandwidth register controls the loop
bandwidth of the PLL used to recover the incoming clock
signal. The default 4MHz setting works well in most
applications, however a lower bandwidth of 1MHz has
proven to work just as well with good TMDS sources and
slightly better with marginal sources.
13
FN6275.5
June 4, 2008