ISL54100_14 Datasheet, PDF (20/21 Pages) Intersil Corporation – TMDS Regenerators with Multiplexers

ISL54100, ISL54101, ISL54102
START Command
ISL5410x Serial Bus
R/W
ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 0
A7
A6
A5
A4
A3
A2
A1
A0
START Command
ISL5410x Serial Bus
R/W
ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 1
Signals the beginning of serial I/O
ISL5410x Device Select Address Write
The first 7 bits of the first byte select the ISL54100 on the 2-wire
bus at the address set by the ADDR[6:0} pins. R/W = 0,
indicating that the next transaction will be a write.
ISL5410x Register Address Write
This sets the initial address of the ISL5410x’s configuration
register for subsequent reading.
Ends the previous transaction and starts a new one
ISL5410x Serial Bus Address Write
This is the same 7-bit address that was sent previously, however
the R/W bit is now a 1, indicating that the next transaction(s) will
be a read.
D7
D6
Signals from
the Host
SDA Bus
Signals from
the ISL5410x
ISL5410x Register Data Read(s)
D5
D4
D3
D2
D1
D0 _{This is the data read from the ISL5410x’s configuration register.}
(Repeat if desired)
Note: The ISL5410x’s Configuration Register’s address pointer
auto increments after each data read: repeat this step to read
multiple sequential bytes of data from the Configuration Register.
STOP Command
Signals the ending of serial I/O
R
S
T _{Serial Bus}
A
R
Address
T
Register
Address
E
S
T _{Serial Bus}
A
R
Address
T
Data
Read*
S
T
O
AP
C
a a a a a a a 0 AAAAAAAA a a a a a a a 1
K
A
A
C
C
A
C
d
d
d
d
d
d
d
d
K
K
K
* The data read step may be repeated to read
from the ISL5410x’s Configuration Register
sequentially, beginning at the Register
Address written in the two steps previous.
FIGURE 18. CONFIGURATION REGISTER READ
Datasheet Changes from FN6275.4
• Added note to description on front page describing specific
HDMI 1.3a features supported. Spelled out TMDS acronym.
• Added additional information to pins 74 and 95, noting that
they are called V_D_ESD pins and should be connected to
V_D_ESD via a Schottky diode.
• Fixed typo on Register 0x05’s Reverse Output Order bit. It
was labelled as bit 4, it is now correctly labelled as bit 3.
• Added TEST pin to Pin Descriptions table.
• Added Note 2 (emphasizing that operation above 165MHz
is not guaranteed) to electrical specs.
• Changed description of register 0x03’s Activity Detect bits
and recommended new settings to improve accuracy of
the activity detect function.
• Added note to recommend Recalibration (register 0x03b7)
after supply and temp have settled.
• Changed recommended PLL Bandwidth (register 0x10)
setting to 1MHz
• Added “Tx Loading Considerations” section on page 16.
• Updated Pb-free note to new verbiage.
• Updated Note 2 to new verbiage.
20
FN6275.5
June 4, 2008