ISL62883 Datasheet, PDF (3/39 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5 Mobile CPUs and GPUs

ISL62883, ISL62883B
Pin Function Description
GND
Signal common of the IC. Unless otherwise stated,
signals are referenced to the GND pin.
PGOOD
Power-Good open-drain output indicating when the
regulator is able to supply regulated voltage. Pull up
externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
PSI#
Low load current indicator input. When asserted low,
indicates a reduced load-current condition. For
ISL62883, when PSI# is asserted low, PWM3 will be
disabled.
RBIAS
147k Resistor to GND sets internal current reference.
VR_TT#
Thermal overload output indicator.
NTC
Thermistor input to VR_TT# circuit.
VW
A resistor from this pin to COMP programs the switching
frequency (8kΩ gives approximately 300kHz).
COMP
This pin is the output of the error amplifier. Also, a
resistor across this pin and GND adjusts the overcurrent
threshold.
FB
This pin is the inverting input of the error amplifier.
ISEN3/FB2
When the ISL62883 is configured in 3-phase mode, this
pin is ISEN3. ISEN3 is the individual current sensing for
phase 3. When the ISL62883 is configured in 2-phase
mode, this pin is FB2. There is a switch between the FB2
pin and the FB pin. The switch is on in 2-phase mode and
is off in 1-phase mode. The components connecting to
FB2 are used to adjust the compensation in 1-phase
mode to achieve optimum performance.
ISEN2
Individual current sensing for Phase-2. When ISEN2 is
pulled to 5V VDD, the controller will disable Phase-2 and
allow other phases to operate.
ISEN1
Individual current sensing for phase 1.
VSEN
Remote core voltage sense input. Connect to
microprocessor die.
RTN
Remote voltage sensing return. Connect to ground at
microprocessor die.
ISUM- and ISUM+
Droop current sense input.
VDD
5V bias power.
VIN
Battery supply voltage, used for feed-forward.
IMON
An analog output. IMON outputs a current proportional to
the regulator output current.
BOOT1
Connect an MLCC capacitor across the BOOT1 and the
PHASE1 pins. The boot capacitor is charged through an
internal boot diode connected from the VCCP pin to the
BOOT1 pin, each time the PHASE1 pin drops below VCCP
minus the voltage dropped across the internal boot
diode.
UGATE1
Output of the Phase-1 high-side MOSFET gate driver.
Connect the UGATE1 pin to the gate of the Phase-1
high-side MOSFET.
PHASE1
Current return path for the Phase-1 high-side MOSFET
gate driver. Connect the PHASE1 pin to the node
consisting of the high-side MOSFET source, the low-side
MOSFET drain, and the output inductor of phase 1.
VSSP1
Current return path for the Phase-1 low-side MOSFET
gate driver. Connect the VSSP1 pin to the source of the
Phase-1 low-side MOSFET through a low impedance
path, preferably in parallel with the trace connecting the
LGATE1 pin to the gate of the Phase-1 low-side MOSFET.
LGATE1
Output of the Phase-1 low-side MOSFET gate driver.
Connect the LGATE1 pin to the gate of the Phase-1 low-
side MOSFET.
PWM3
PWM output for Channel 3. When PWM3 is pulled to 5V
VDD, the controller will disable Phase-3 and allow other
phases to operate.
VCCP
Input voltage bias for the internal gate drivers. Connect
+5V to the VCCP pin. Decouple with at least 1µF of an
MLCC capacitor to VSSP1 and VSSP2 pins respectively.
LGATE2
Output of the Phase-2 low-side MOSFET gate driver.
Connect the LGATE2 pin to the gate of the Phase-2 low-
side MOSFET.
3
FN6891.2
February 25, 2010