ISL62883 Datasheet, PDF (16/39 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5 Mobile CPUs and GPUs

ISEN3
INTERNAL
TO IC
ISEN2
ISEN1
V3p
Phase3
Rs
Rs
Cs
Rs
V2p
Phase2
Rs
Rs
Cs
Rs
V1p
Phase1
Rs
Rs
Cs
Rs
ISL62883, ISL62883B
L3 Rdcr3 _Rpcb3
IL3 _V3n
L2 Rdcr2 _{Rpcb2 Vo}
IL2 _V2n
Current balancing (I_L1 = I_L2 = I_L3) will be achieved
when there is R_dcr1 = R_dcr2 = R_dcr3. R_pcb1, R_pcb2 and
R_pcb3 will not have any effect.
REP RATE = 10kHz
L1 Rdcr1 _Rpcb1
IL1 _V1n
REP RATE = 25kHz
FIGURE 11. DIFFERENTIAL-SENSING CURRENT
BALANCING CIRCUIT
Sometimes, it is difficult to implement symmetrical
layout. For the circuit shown in Figure 10, asymmetric
layout causes different R_pcb1, R_pcb2 and R_pcb3 thus
current imbalance. Figure 11 shows a differential-sensing
current balancing circuit recommended for ISL62883.
The current sensing traces should be routed to the
inductor pads so they only pick up the inductor DCR
voltage. Each ISEN pin sees the average voltage of three
sources: its own phase inductor phase-node pad, and the
other two phases inductor output side pads. Equations 8
thru 10 give the ISEN pin voltages:
V_ISEN1 = V_1p + V_2n + V_3n
(EQ. 8)
V_ISEN2 = V_1n + V_2p + V_3n
(EQ. 9)
V_ISEN3 = V_1n + V_2n + V_3p
(EQ. 10)
The ISL62883 will make V_ISEN1 = V_ISEN2 = V_ISEN3 as
in:
V_1p + V_2n + V_3n = V_1n + V_2p + V_3n
(EQ. 11)
REP RATE = 50kHz
REP RATE = 100kHz
V_1n + V_2p + V_3n = V_1n + V_2n + V_3p
Rewriting Equation 11 gives:
V_1p – V_1n = V_2p – V_2n
and rewriting Equation 12 gives:
V_2p – V_2n = V_3p – V_3n
Combining Equations 13 and 14 gives:
V_1p – V_1n = V_2p – V_2n = V_3p – V_3n
Therefore:
R_dcr1 × I_L1 = R_dcr2 × I_L2 = R_dcr3 × I_L3
(EQ. 12)
REP RATE = 200kHz
(EQ. 13)
(EQ. 14)
(EQ. 15)
(EQ. 16)
FIGURE 12. ISL62883 EVALUATION BOARD CURRENT
BALANCING DURING DYNAMIC
OPERATION. CH1: IL1, CH2: I_LOAD, CH3:
IL2, CH4: IL3
16
FN6891.2
February 25, 2010