ISL62883 Datasheet, PDF (26/39 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5 Mobile CPUs and GPUs

ISL62883, ISL62883B
Optional Slew Rate Compensation Circuit
For 1-Tick VID Transition
Rdroop
Rvid Cvid
FB
Ivid
Vcore
OPTIONAL
Idroop_vid
COMP
E/A
Σ
DAC
VDAC
X1
INTERNAL
TO IC
VIDs
VID<0:6>
RTN
VSSSENSE
VSS
VID<0:6>
Vfb
Ivid
Vcore
Idroop_vid
FIGURE 25. OPTIONAL SLEW RATE COMPENSATION
CIRCUIT FOR1-TICK VID TRANSITION
During a large VID transition, the DAC steps through the
VIDs at a controlled slew rate of 2.5µs per tick (12.5mV),
controlling output voltage V_core slew rate at 5mV/µs.
Figure 25 shows the waveforms of 1-tick VID transition.
During 1-tick VID transition, the DAC output changes at
approximately 15mV/µs slew rate, but the DAC cannot
step through multiple VIDs to control the slew rate.
Instead, the control loop response speed determines
V_core slew rate. Ideally, V_core will follow the FB pin
voltage slew rate. However, the controller senses the
inductor current increase during the up transition, as the
I_{droop_vid} waveform shows, and will droop the output
voltage V_core accordingly, making V_core slew rate slow.
Similar behavior occurs during the down transition.
To control V_core slew rate during 1-tick VID transition,
one can add the R_vid-C_vid branch, whose current I_vid
cancels I_{droop_vid}.
When V_core increases, the time domain expression of the
induced I_droop change is expressed in Equation 43:
I_droop(t)
=
-^C----^o---^u----^t---^×----^L----^L--
R_droop
×
-^d---^V-----^c---^o---^r--^e-
dt
×
⎛
⎜
⎜
1
⎝
–
e ^{C-----o----u---–-t--t-×-----L---L--}_{⎟⎟⎞}
⎠
(EQ. 43)
where C_out is the total output capacitance.
In the mean time, the R_vid-C_vid branch current I_vid time
domain expression is shown in Equation 44:
I_vid(t)
=
C_vid
×
d_----V_-----f-b--
dt
×
⎛
⎜
⎜
1
–
e ^{R-----v----i-d----–-×---t--C-----v---i--d--}_{⎟⎟⎞}
⎝
⎠
(EQ. 44)
It is desired to let I_vid(t) cancel I_{droop_vid}(t). So there
are:
C_v
i
d
×
d_----V_-----f-b--
dt
=
-^C----^o---^u----^t---^×-----^L---^L--
R_droop
×
-^d---^V-----^c---^o---^r--^e-
dt
(EQ. 45)
and:
R_vid × C_vid = C_out × LL
(EQ. 46)
The result is expressed in Equation 47:
R_vid = R_droop
(EQ. 47)
and:
C_vid
=
C_{-----o---u----t---}×_----L_----L_--
×
-^d---^V-----^c---^o---^r--^e-
--------^d---^t--------
R_droop
d_----V_-----f-b--
dt
(EQ. 48)
For example: given LL = 1.9mΩ, R_droop = 2.37kΩ,
C_out = 1320µF, dV_core/dt = 5mV/us and
dV_fb/dt = 15mV/µs, Equation 47 gives R_vid = 2.37kΩ
and Equation 48 gives C_vid = 350pF.
It’s recommended to select the calculated R_vid value and
start with the calculated C_vid value and tweak it on the
actual board to get the best performance.
During normal transient response, the FB pin voltage is
held constant, therefore is virtual ground in small signal
sense. The R_vid-C_vid network is between the virtual
ground and the real ground, and hence has no effect on
transient response.
Voltage Regulator Thermal Throttling
54uA 64uA
NTC
+
V_{NTC RNTC}
-
R_s
1.24V
SW1
VR_TT#
-
+
SW2
1.20V
INTERNAL TO
ISL62882
FIGURE 26. CIRCUITRY ASSOCIATED WITH THE
THERMAL THROTTLING FEATURE OF THE
ISL62882
26
FN6891.2
February 25, 2010