ISL6260CCRZ Datasheet, PDF (3/28 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6+ Mobile CPUs

ISL6260C
PWM3
PWM output for channel 3. When PWM3 is pulled to 5V
VDD, PWM3 will be disabled and allow other channels to
operate.
PWM2
PWM output for channel 2. For ISL6260C, PSI# low will
make this output tri-state. When PWM2 is pulled to 5V VDD,
PWM2 will be disabled and allow other channels to operate.
PWM1
PWM output for channel 1.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VID input with VID0 = LSB and VID6 = MSB.
CLK_EN#
Digital output to enable System PLL Clock; Goes active after
13 switching cycles after Vcore is within 10% of Boot
Voltage.
PGOOD
Power Good open-drain output. Will be pulled up externally
by a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
3V3
3.3V supply voltage for CLK_EN# logic, such an
implementation will improve power consumption from 3.3V
compared to open drain circuit other wise.
VR_ON
Voltage Regulator enable input. A high level logic signal on
this pin enables the regulator.
DPRSLPVR
Deeper Sleep Enable signal. At steady state, a high level
logic signal on this pin indicates that the micro-processor is
in Deeper Sleep Mode. Between active and sleep mode
transition, high logic level on this pin programs slow C4 entry
and exit; low logic level on this pin programs large charging
or discharging soft pin current, and therefore fast output
voltage transition slew rate.
DPRSTP#
Deeper Sleep Enable signal. A low level logic signal on this
pin indicates that the micro-processor is in Deeper Sleep
Mode.
3
FN9259.3
June 21, 2010