ISL6260CCRZ Datasheet, PDF (24/28 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6+ Mobile CPUs

ISL6260C
10uA
OC
-
+
Internal to
ISL6260
+
1
+
-
Σ
+
1
+
-
OCSET
+
DROOP
-
VSUM
DFB
DROOP
VSUM
+
VN
-
RS _EQV
= ^RS
N
Vdcr _EQV
= Iout × ^DCR
N
Rn
=
(Rntc
(Rntc
+ Rseries )× Rpar
+ Rseries ) + Rpar
VDIFF
RTN
VSEN VO'
VO'
RO _EQV
= ^RO
N
FIGURE 47. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DCR SENSING
We do this using the assumption that we desire
approximately a 0.57 gain from the DCR voltage, Vdcr, to the
Rn network. We call this gain, G1.
G1 = 0.57
(EQ. 10)
After simplification, then RS_EQV is given by Equation 11:
RS_EQV
=
⎛
⎝
---¹----
G1
–
1_⎠⎞
R
n
=
2.56 k Ω
(EQ. 11)
The individual resistors from each phase to the VSUM node,
labeled RS1, RS2 and RS3 in Figure 46, are then given by
Equation 12, where N is 3, for the number of channels in
active operation.
RS = N × RS_EQV = 7.69kΩ
(EQ. 12)
Choosing RS = 7.68k_1% is a good choice. Once we know
the attenuation of the RS and RN network, we can then
determine the Droop amplifier Gain required to achieve the
load line. Setting Rdrp1 = 1k_1%, then Rdrp2 is can be
found using Equation 13.
Rdrp2 = _⎝⎛-^N-_D----^×-_C----^R-_R----^d--_×--^r--^o-_G---^o--₁--^p-- – 1_⎠⎞ × Rdrp1
(EQ. 13)
Setting N = 3 for 3 channel operation, Droop Impedance
(Rdroop) = 0.0021 (V/A) as per the Intel IMVP-6+
specification, DCR = 0.0012Ω typical, Rdrp1 = 1kΩ and the
attenuation gain (G1) = 0.57, Rdrp2 is then:
Rdrp2 = _{⎝⎛0}----_.-³⁰----₀-^×--₁--⁰-₂---^.-⁰-_×---⁰--₀-²--_.-¹-₅----₇- – 1_⎠⎞ × 1K = 8.21kΩ
(EQ. 14)
Rdrp2 is selected to be a 8.25k_1% resistor. Note, we
choose to ignore the RO resistors because they do not add
significant error.
These values are extremely sensitive to layout and coupling
factor of the NTC to the inductor. As only one NTC is
required in this application, this NTC should be placed as
close to the Channel 1 inductor as possible. And very
importantly, the PCB traces sensing the inductor voltage
should be go directly to the inductor pads.
Once the board has been laid out, some adjustments may
be required to adjust the full load droop voltage. This can be
accomplished by allowing the system to achieve thermal
equilibrium at full load, and then adjusting Rdrp2 to obtain
the appropriate load line slope.
To see whether the NTC has compensated the temperature
change of the DCR, the user can apply full load current and
wait for the thermal steady state and see how much the
output voltage will deviate from the initial voltage reading. A
good NTC thermistor compensation can limit the output
voltage drift to 2mV. If the output voltage is decreasing with
temperature increase, that ratio between the NTC thermistor
value and the rest of the resistor divider network has to be
increased. Users should use the ISL6260C evaluation board
component values and follow the evaluation board layout of
NTC as much as possible to minimize engineering time.
The 2.1mV/A load line should be adjusted by Rdrp2 based on
maximum current steps, not based on small current steps.
Basically, if the max current is 40A, the required droop voltage
is 84mV with 2.1mΩ load line impedance. The user should
have 40A load current on the converter and look for 84mV
droop. If the droop voltage is less than 84mV, for example,
80mV. The new value will be calculated by Equation 15:
24
FN9259.3
June 21, 2010