ISL6260CCRZ Datasheet, PDF (20/28 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6+ Mobile CPUs

ISL6260C
TABLE 3. SUMMARY OF THE FAULT PROTECTION AND RESET OPERATIONS OF ISL6260C
FAULT DURATION
PRIOR TO
PROTECTION
PROTECTION
ACTIONS
FAULT RESET
Overcurrent
120µs
PWMs tri-state, PGOOD latched low
VR_ON toggle or VDD toggle
Way-Overcurren (2.5X OC) <2µs
PWMs tri-state, PGOOD latched low
VR_ON toggle or VDD toggle
Overvoltage 1.7V
Immediately
Low side MOSFET on until Vcore <0.85V, then PWM
tri-state, PGOOD latched low.
VDD toggle
Overvoltage +200mV
1ms
PWMs tri-state, PGOOD latched low
VR_ON toggle or VDD toggle
Undervoltage -300mV
1ms
PWMs tri-state, PGOOD latched low
VR_ON toggle or VDD toggle
Phase Current Unbalance 1ms
PWMs tri-state, PGOOD latched low
VR_ON toggle or VDD toggle
Over Temperature
Immediately
VR_TT# goes low
N/A
The ISL6260C has a thermal throttling feature. If the voltage
on the NTC pin goes below the 1.18V OT threshold, the
VR_TT# pin is pulled low indicating the need for thermal
throttling to the system oversight processor. No other action
is taken within the ISL6260C in response to NTC pin voltage.
Fault protection is summarized in Table 3.
Power Monitor
The power monitor signal is an analog output. Its magnitude
is proportional to the product of V_CCSENSE and the voltage
difference between V_DROOP and V_O, which is the
programmed load line impedance (2.1mΩ) multiplied by load
current. The output voltage of the PMON pin is given by:
V_PMON = V_CCSENSE*(V_DROOP-V_O)*17.5 (Volt)
The power consumed by the CPU can be calculated by:
Pcpu = V_PMON/(17.5*0.0021) (Watt)
where the 0.0021 is the load line impedance.The power
monitor load regulation is about 7Ω. Basically, within its
sourcing/sinking current capability range, when the power
monitor loading changes 1mA, the output of the power
monitor will change 7mV. The 7Ω impedance is associated
with the layout and packaging resistance of PMON pin inside
the IC. Compared to the load resistance on the power
monitor pin in practical applications, 7Ω output impedance
contributes no significance of error.
Component Selection and Application
Soft-Start and Mode Change Slew Rates
The ISL6260C uses 2 slew rates for various modes of
operation. The first is a slow slew rate, used to reduce inrush
current on start-up. It is also used to reduce audible noise
when entering or exiting Deeper Sleep Mode. A faster slew
rate is used to exit out of Deeper Sleep and to increase
system performance by achieving active mode regulation
more quickly. Note that the SOFT cap current is bidirectional
and is flowing into the SOFT capacitor when the output
voltage is commanded to rise, and out of the SOFT capacitor
when the output voltage is commanded to fall.
The two slew rates are determined by the currents into the
SOFT pin. As can be seen in Figure 44, the SOFT pin has a
capacitance to ground. Also, the SOFT pin is the input to the
error amplifier and is, therefore, the commanded system
voltage. Depending on the state of the system, i.e. Start-Up
or Active mode, and the state of the DPRSLPVR pin, one of
the two currents shown in Figure 44 will be used to charge or
discharge this capacitor, thereby controlling the slew rate of
the commanded voltage. These currents can be found under
the Soft Current section of the “Electrical Specifications”
table on page 4.
ISL6260C
I_SS
SOFT
I₂ ERROR
AMPLIFIER
+
C_SOFT
+
V_REF
FIGURE 44. SOFT PIN CURRENT SOURCES FOR FAST AND
SLOW SLEW RATES
The first current, labeled I_SS, is given in the Specification
Table as 42µA. This current is used during Soft-Start. The
second current, I₂ sums with I_SS to get the large current
labeled I_GV in the “Electrical Specifications” table on page 4.
This total current is typically 205µA with a minimum of
180µA.
The IMVP-6+™ specification reveals the critical timing
associated with regulating the output voltage. The symbol,
Slewrate, as given in the IMVP-6+™ specification, will
20
FN9259.3
June 21, 2010