ISL6260CCRZ Datasheet, PDF (10/28 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6+ Mobile CPUs

ISL6260C
Typical Operating Performance (Continued)
V_OUT
COMP PIN
FIGURE 19. TRANSIENT LOAD RESPONSE, 40A LOAD STEP
@ 200A/µs, 3 PHASE
FIGURE 20. TRANSIENT LOAD 3 PHASE OPERATION -
CURRENT BALANCE
FIGURE 21. TRANSIENT LOAD 3 PHASE OPERATION, ZOOM
OF RISING EDGE CURRENT BALANCE
VID MSB
V_OUT
FIGURE 22. TRANSIENT LOAD 3 PHASE OPERATION, ZOOM
OF FALLING EDGE CURRENT BALANCE
VID MSB
V_OUT
FIGURE 23. IVID MSB BIT CHANGE FROM 1.4375V TO 0.65V
SHOWING 9mV/µs SLEW RATE, DPRSLPVR = 0,
DPRSTP# = 1
10
FIGURE 24. SLEW RATE ENTERING C4, VID MSB BIT
CHANGE FROM 1.4375V TO 0.65V SHOWING
2mV/µs SLEW RATE, DPRSLPVR = 1, DPRSTP# = 0
FN9259.3
June 21, 2010