ISL6260CCRZ Datasheet, PDF (23/28 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6+ Mobile CPUs

ISL6260C
IS E N 1
IS E N 2
IS E N 3
IS E N 1
OC
IS E N 2
10uA
-
+
Internal to
IS L 6 2 6 0
+
Σ
+
V D IF F
1
+
-
1
+
-
RTN
0 .2 2 u F
IS E N 3
OCSET
+
DROOP
-
VSUM
DFB
DROOP
R _OCSET
VO'
VSUM
VSEN
VO'
VO'
0.01uF
10
Ropn1
to Vout
Ropn2
VCC_SENSE
VSS_SENSE
To Processor
Socket Kelvin
C o n n e c tio n s
I_phase1
RS1
VSUM
I_phase2
RS2
VSUM
I_phase3
VSUM
RS3
L₁
R _L1
+ ^Vdcr1-
DCR
C _L1
RO1
IS E N 1
L₂
R_L2
VO'
DCR
+ ^Vdcr2 -
RO2
IS E N 2
L₃
R_L3
IS E N 3
C _L2
VO'
+ ^Vdcr3-
DCR
C _L3
VO'
RO3
Vout
C _bulk
ESR
FIGURE 46. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DCR SENSING
Static Mode of Operation - Static Droop using DCR
Sensing
As previously mentioned, the ISL6260C has an internal
differential amplifier which provides for extremely accurate
voltage regulation at the die of the processor. The load line
regulation is also very accurate, and the process of selecting
the components for the appropriate load line droop is
explained here.
For DCR sensing, the process of compensation for DCR
resistance variation to achieve the desired load line droop
has several steps and is somewhat iterative.
In Figure 46 we show a 3 phase solution using DCR
sensing. There are two resistors around the inductor of each
phase. These are labeled RS and RO. These resistors are
used to sense the DC voltage drop across each inductor.
Each inductor will have a certain level of DC current flowing
through it, this current when multiplied by the DCR of the
inductor creates a small DC level of voltage. When this
voltage is summed with the other channels DC voltages, the
total DC load current can be derived.
RO is typically 5Ω to 10Ω. This resistor is used to tie the
outputs of all channels together and thus create a summed
average of the local CORE voltage output. RS is determined
through an understanding of both the DC and transient load
currents. This value will be covered in the next section.
However, it is important to keep in mind that the output of
each of these RS resistors are tied together to create the
VSUM voltage node. With both the outputs of RO and RS
tied together, the simplified model for the droop circuit can
be derived. This is presented in Figure 47.
Figure 47 shows the simplified model of the droop circuitry.
Essentially one resistor can replace the RO resistors of each
phase and one RS resistor can replace the RS resistors of
each phase. The total DCR drop due to load current can be
replaced by a DC source, the value of which is given by
Equation 8.
Vdcr_EQV
=
-^I-^O-----^U----^T-----^×-----^D----^C-----^R---
N
(EQ. 8)
where N is the number of channels designed for active
operation. Another simplification was done by reducing the
NTC network comprised of Rntc, Rseries and Rparallel,
given in Figure 46, to a single resistor given as Rn as shown
in Figure 47.
The first step in droop load line compensation is to adjust
Rn, RO_EQV and RS_EQV such that sufficient droop voltage
exists even at light loads between the VSUM and VO’ nodes.
We recognize that these components form a voltage divider.
As a rule of thumb we start with the voltage drop across the
Rn network, VN, to be 0.57 x Vdcr. This ratio provides for a
fairly reasonable amount of light load signal from which to
arrive at droop.
First we calculate the equivalent NTC network resistance,
Rn. Typical values that provide good performance are,
Rseries = 3.57k_1%, Rpar = 4.53k_1% and Rntc = 10kΩ
NTC, ERT-J1VR103J from Panasonic. Rn is then given by
Equation 9.
Rn
=
(_---R_-----s_---e_----r_---i_-e_----s_-----+----R_-----n_----t_--c_----)_---×_-----R_-----p_----a_----r
Rseries + Rntc + Rpar
=
3.4 k Ω
(EQ. 9)
In our second step we calculate the series resistance from
each phase to the Vsum node, labeled RS1, RS2 and RS3
in Figure 46.
23
FN9259.3
June 21, 2010