ISL6260CCRZ Datasheet, PDF (17/28 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6+ Mobile CPUs

ISL6260C
Theory of Operation
Operational Description
The ISL6260C is a multiphase regulators implementing
Intel® IMVP-6+ protocol. It can be programmed for one-,
two- or three-channel operation for microprocessor core
applications up to 70A. With ISL6208 gate driver capable of
diode emulation, the ISL6260C provides optimum efficiency
in both heavy and light conditions.
ISL6260C uses Intersil patented R³ (Robust Ripple
Regulator™) modulator. The R³ modulator combines the
best features of fixed frequency PWM and hysteretic PWM
while eliminating many of their shortcomings. The ISL6260C
modulator internally synthesizes analog signals inside the IC
emulating the inductor ripple currents and use hysteretic
comparators on those signals to determine switching pulse
widths. Operating on these large-amplitude, noise-free
synthesized signals allows the ISL6260C to achieve lower
output ripple and lower phase jitter than conventional
hysteretic and fixed PWM mode controllers. Unlike
conventional hysteretic converters, the ISL6260C has an
error amplifier that allows the controller to maintain a 0.5%
output voltage accuracy. At heavy load conditions, the
ISL6260 is switching at a relatively constant switching
frequency similar to fixed frequency PWM controller. At light
load conditions, the ISL6260C is switching at a frequency
proportional to load current similar to hysteretic mode
controller.
ISL6260C disables PWM2 when PSI# is asserted low. And
the power monitor pin provides an analog signal
representing the output power of the converter.
Start-up Timing
With the controller's +5V V_DD voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic HIGH threshold. Approximately
120µs later SOFT and V_OUT start ramping up to the boot
voltage of 1.2V. During this interval, the SOFT capacitor is
charged with approximately 40µA. Therefore, if the SOFT
capacitor is selected to be 20nF, the SOFT ramp will be at
about 2mV/µs for a soft-start time of 600µs. Once V_OUT
(VDIFF) is within 10% of the boot voltage for 13 PWM cycles
(43µs for frequency = 300kHz), then CLK_EN# is pulled
LOW and the SOFT capacitor is charged up with
approximately 200µA. Therefore, V_OUT slews at +10mV/µs
to the voltage set by the VID pins. Approximately 7ms later,
PGOOD is asserted HIGH. A typical start-up timing is shown
in Figure 42. Similar results occur if VR_ON is tied to V_DD,
with the soft-start sequence starting 120µs after V_DD
crosses the POR threshold.
V_DD
VR_ON
120µs
SOFT & VO
10mV/µs
2mV/µs
VBOOT
90%
VID COMMANDED
VOLTAGE
13 SWITCHING CYCLES
CLK_EN#
IMVP-6+ PGOOD
~7ms
FIGURE 42. SOFT-START WAVEFORMS USING A 20nF SOFT
CAPACITOR
Static Operation
A) Voltage Regulation at Zero Load Current
After the start sequence, the output voltage will be regulated
to the value set by the VID inputs per Table 1. The entire VID
Table is presented in the Intel IMVP-6+™ specification. The
ISL6260C will control the no-load output voltage to an
accuracy of ±0.5% over the range of 0.75V to 1.5V.
TABLE 1. TRUNCATED VID TABLE FOR INTEL IMVP-6+™
SPECIFICATION
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOUT
0
0
0
0
0
0
0 1.500V
0
0
0
0
0
0
1 1.4875
0
0
0
0
1
0
1 1.4375
0
0
0
0
1
1
1 1.4125
0
0
0
1
0
0
0 1.4000
0
0
1
0
0
0
1 1.2875
0
0
1
1
0
0
0 1.2000
0
0
1
1
1
0
0 1.1500
0
1
0
1
0
0
0 1.0000
0
1
0
1
0
1
1 0.9625
0
1
1
1
1
0
0 0.7500
1
0
0
0
1
0
0 0.6500
1
0
1
0
0
0
0 0.5000
1
1
0
0
0
0
0 0.300
1
1
0
0
0
0
1
Off
1
1
0
0
0
1
0
Off
...
Off
1
1
1
1
1
1
0
Off
1
1
1
1
1
1
1
Off
17
FN9259.3
June 21, 2010