ISL6260CCRZ Datasheet, PDF (25/28 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6+ Mobile CPUs

ISL6260C
Rdrp 2 _ new = ^{84 mV} (Rdrp 1 + Rdrp 2 ) − Rdrp 1
80 mV
(EQ. 15)
For the best accuracy, the equivalent resistance on the DFB
and VSUM pins should be identical so that the bias current
of the droop amplifier does not cause an offset voltage. In
the example above, the resistance on the DFB pin is Rdrp1
in parallel with Rdrop2, that is, 1k in parallel with 8.21k or
890Ω. The resistance on the VSUM pin is Rn in parallel with
RS_EQV or 3.4k in parallel with 2.56k or 1460Ω. The
mismatch in the effective resistances is 1460 - 890 = 570Ω.
To reduce the mismatch, multiply both Rdrp1 and Rdrp2 by
the appropriate factor. The appropriate factor in the example
is 1460/890 = 1.64.
Dynamic Mode of Operation - Dynamic Droop
using DCR Sensing
Droop is very important for load transient performance. If the
system is not compensated correctly, the output voltage
could sag excessively upon load application and potentially
create a system failure. The output voltage could also take a
long period of time to settle to its final value.
The L/DCR time constant of the inductor must be matched to
the Rn*Cn time constant as shown in Equation 16:
------^L-------
DCR
=
⎛
⎜
⎝
-_RR----_nn-----+^×-----^RR-----^SS----^EE----^QQ----^VV--_{⎠⎟⎞}
× Cn
(EQ. 16)
Solving for Cn we now have Equation 17:
------^L-------
Cn = --------------^D-----^C-----^R----------------
⎛
⎜
⎝
-_RR----_nn-----+^×-----^RR-----^SS----^EE----^QQ----^VV--_{⎠⎟⎞}
(EQ. 17)
Note, RO was neglected. As long as the inductor time
constant matches the droop circuit RC time constants as
given above, the transient performance will be optimum. The
selection of Cn may require a slight adjustment to correct for
layout inconsistencies and component tolerance. For the
example of L = 0.5µH, Cn is calculated in Equation 18.
-⁰---^.--⁵----^μ----^H---
Cn = ----------------⁰---^.--⁰---⁰----¹---²----------------- = 28.5nF
⎛
⎝
3^-3---..^--44^---kk^----ΩΩ^{------+×-----22---..--55---66----kk---ΩΩ--- ⎠⎞}
(EQ. 18)
The value of this capacitor is selected to be 27nF. As the
inductors tend to have 20% to 30% tolerances, this cap
generally will be tuned on the board by examining the
transient voltage. If the output voltage transient has an initial
dip, lower than the voltage required by the load line, and is
slowly increasing back to the steady state, the cap should be
increased and vice versa. It is better to have the cap value a
little bigger to cover the tolerance of the inductor to prevent
the output voltage from going lower than the spec. This cap
needs to be a high grade cap like X7R with low tolerance.
There is another consideration in order to achieve better
time constant match mentioned above. The NPO/COG
(class-I) capacitors have only 5% tolerance and a very good
thermal characteristics. But those caps are only available in
small capacitance values. In order to use such capacitors,
the resistors and thermistors surrounding the droop voltage
sensing and droop amplifier has to be resized up to 10x to
reduce the capacitance by 10x. But attention has to be paid
in balancing the impedance of droop amplifier in this case.
Dynamic Mode of Operation - Compensation
Parameters
Considering the voltage regulator as a black box with a
voltage source controlled by VID and a series impedance, in
order to achieve the 2.1mV/A load line, the series
impedance inside the black box needs to be 2.1mΩ. The
compensation design has to ensure the output impedance of
the converter be lower than 2.1mΩ. There is a mathematical
calculation file available to the user. The power stage
parameters such as L and Cs are needed as the input to
calculate the compensation component values. Attention
has be paid to the input resistor to the FB pin. Too high of a
resistor will cause an error to the output voltage regulation
because of bias current flowing in the FB pin. It is better to
keep this resistor below 3k when using this file.
Static Mode of Operation - Current Balance using
DCR or Discrete Resistor Current Sensing
Current Balance is achieved in the ISL6260C through the
matching of the voltages present on the ISEN pins. The
ISL6260C adjusts the duty cycles of each phase to maintain
equal potentials on the ISEN pins. RL and CL around each
inductor, or around each discrete current resistor, are used
to create a rather large time constant such that the ISEN
voltages have minimal ripple voltage and represent the DC
current flowing through each channel’s inductor. For
optimum performance, RL is chosen to be 10kΩ and CL is
selected to be 0.22µF. When discrete resistor sensing is
used, a capacitor of 10nF should be placed in parallel with
RL to properly compensate the current balance circuit.
ISL6260C uses RC filter to sense the average voltage on
phase node and forces the average voltage on the phase
node to be equal for current balance. Even though the
ISL6260C forces the ISEN voltages to be almost equal, the
inductor currents will not be exactly the same. Take DCR
current sensing as example, two errors have to be added to
find the total current imbalance. 1) Mismatch of DCR: If the
DCR has a 5% tolerance, then the resistors could mismatch
by 10% worst case. If each phase is carrying 20A then the
phase currents mismatch by 20A*10% = 2A. 2) Mismatch of
phase voltages/offset voltage of ISEN pins. The phase
voltages are within 2mV of each other by current balance
circuit. The error current that results is given by 2mV/DCR. If
DCR = 1mΩ then the error is 2A.
In the above example, the two errors add to 4A. For a two
phase DC/DC, the currents would be 22A in one phase and
18A in the other phase. In the above analysis, the current
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FN9259.3
June 21, 2010