ISL1801 Datasheet, PDF (3/30 Pages) Intersil Corporation – sPMIC for Micro Converter Bias and Drivers

Block Diagram
ISL1801
BRESET
BCMD
PVCC3
BDRIVE
PGND4
DRIVE3
PGND3
PWM3
PHASE3
OCSET3
PVCC3
PVCC3
ISEN
LATCHRPT
120µA
CMP2+
CMP2-
GND
CMP2
CMP1+
CMP1-
CMP1
CMP1O
RPWM3
PGOOD2
ENABLE
FF3
Q ^SET S
Q CLR R
ENABLE
FF2
CL
S ^SET Q
R CLR Q
ONE
SHOT
S ^SET Q
R CLR Q
FF1
7V
PVCC3
0.5*VDDREF
UVLO
LDO1
OC, OV,
OT, SS
LEVEL
SHIFT
PWM
Logic
VCC1
Q ^SET S
Q CLR R
PVCC3
LDO2
POR
VREF1
ON-TIME
CONTROL
FB2
GND
DELAY
VDDREF
VREF2*0.88
-
VREF2
+
ON-TIME
CONTROL
VCC5V
S ^SET Q
R CLR Q
PWM
Logic
VCC5V
SS, OC, OV, OT
VCC1
VIN1
AGND
BOOT1
PHASE1
PGND1
FB1
TON1
VCC5V
GND
TON2
BOOT2
VIN2
PHASE2
PGND2
AMPO
AMP-
AMP+
SGND
WDO _WATCHDOG
VDDREF
GND
PRE-LOAD
CONTROL
GND
FIGURE 2. ISL1801 BLOCK DIAGRAM
WDI
TIMER
PRELOAD
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July 24, 2014