ISL1801 Datasheet, PDF (23/30 Pages) Intersil Corporation – sPMIC for Micro Converter Bias and Drivers

ISL1801
t₅: When PVCC3 goes above V_th2 again, slowly apply the
preload current to VR1 output.
t₆: If PVCC3 stays above V_th2 after the maximum preload
current is applied the TIMER voltage is pulled to 0V for
1.5ms and released; the external R-C causes the TIMER pin
voltage to ramp up.
t₇: TIMER voltage reaches its 90% threshold; starts to remove
preload step-by-step; from now on, PVCC3 and FB1 are not
monitored for shut-down. Only VCC5V is monitored for
undervoltage lock out (UVLO).
VIN1
t₈: Preload is removed; VR2 starts to ramp up.
t₉: FB2 reaches 90% of its final value; PGOOD2 open-drain
switch is open to allow PGOOD2 to rise.
t₁₀: PGOOD2 is high; all internal circuits, including driver,
OPAMP and comparators are enabled.
NOTE: VR1 current limiting level will ramp up step-by-step with a 25%
increase for each step. The preload will be applied only after the VR1
current limiting level reaches its final value and FB1 is above V_th3.
Pre_load
OFF
PWM1
PVCC3
V_th2
Timer
LDO2
ON
VCC5V
POR
PWM2
Vout2
OFF
4.5V
PGOOD2
OPAMP,
COMPARATOR
Enabled
Disabled
DRIVER3/
BDRIVE
PWM3
Enabled
GND
GND
Disabled
t₀
t₁
t₂
t₃
FIGURE 27. POWER-DOWN SEQUENCE
Power-Down Sequence
Before t₀, the system runs in normal mode:
t₀: PVCC3 drops below V_th2, both drivers’ outputs are pulled to
GND; MCU should stop sending PWM signal; both VR1 and
VR2 continue operating.
t₁: PVCC3 returns above V_th2, both drivers are ready to run.
t₂: PVCC3 drops below V_th2, both drivers’ outputs are pulled to
GND; both VR1 and VR2 continue operating.
t₃: PVCC3 drops to a very low level and VCC5V drops below the
POR level (4.5V); the IC shuts down and all internal circuits
are disabled.
When VCC1 drops below 6V, the VR1 power stage stops
operating. The VR1 control circuit will still run until VCC5V drops
below the 90% * VCC5 (4.5V) POR threshold.
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FN8259.1
July 24, 2014