ISL1801 Datasheet, PDF (19/30 Pages) Intersil Corporation – sPMIC for Micro Converter Bias and Drivers

ISL1801
LATCHRPT
RPWM3
PWM3
CMP1O
CMP2O
ISL1801
ON
SHOT
S ^SET Q
120µA
Q ^SET S
FF2
Q CLR R
OCSET
R1
C1
PGND3
R CLR Q ^FF1
POR
S3 PHASE3
I1
PVCC3
DRIVE3
Q1
PGND3
FIGURE 18. LOW-SIDE DRIVER LOGIC
Once the overcurrent protection is triggered flip-flop FF2 is set
forcing DRIVE3 low. RPWM3 or PWM3 must be pulled low to
reset an OCP event. Since the set input of flip-flop FF2 overrides
the reset input, DRIVE3 is always held low in an overcurrent
condition even if RWPM3 = 0.
The OCP flip-flop output also triggers a one-shot block to
generate a narrow pulse setting LATCHRPT low for 1µs.
For normal operation an OCP event terminates the DRIVE3 on state
early by forcing DRIVE3 to PGND3. The OCP event is reset by setting
PWM3 = 0. This allows DRIVE3 to be turned on by the following
PWM3 = 1 pulse. However, special attention is needed for long-term
or continuous OCP operation. If the OCP is continuously triggered
with RPWM3 = 0 and PWM3 = 1, then a very high switching
frequency may occur on the DRIVE3 pin. Referring to Figure 18 the
following sequence of events will lead to this oscillation. When I1 is
larger than the preset OCP level, it may trigger OCP immediately
when DRIVE3 = 1. Once OCP is triggered, DRIVE3 is pulled low, and
S3 is turned off setting the OCP comparator output low. Since
RPWM3 = 0, the flip-flop FF2 is reset immediately. However, the 1µs
one-shot will keep LATCHRPT low for at least 1µs forcing the DRIVE3
pin low for at least 1µs. After 1µs DRIVE3 is forced high resulting in
another OCP. This operation repeats until PWM3 = 0, RPWM3 = 1 or
I1 drops below the OCP threshold. This condition may result in a
100kHz switching frequency at DRIVE3.
BDRIVE CONTROL LOGIC
The BDRIVE pin is controlled by the BCMD signal. When
BCMD = 1, the BDRIVE output is connected to PVCC3 by its upper
switch. When BCMD = 0 the BDRIVE pin is connected to PGND4
through its lower switch.
When any fault condition occurs, the LATCHRPT signal is set low.
It will also set flip-flop FF3 and connect the BDRIVE pin to PGND4
until flip-flop FF3 is reset by setting BRESET = 1. BDRIVE is held
at PGND4 prior to POR. The BDRIVE logic is shown in Figure 19.
FIGURE 19. BDRIVE CONTROL LOGIC
When VDDREF is not applied during the start, the output of the
level shift block is undefined. In order to prevent BDRIVE turning
on by mistake, it’s recommended adding some offset (~50mV)
on VDDREF pin to make the POR AND gate output low.
Dual High-Speed Comparator
The ISL1801 has two high-speed comparators for fault detection.
The output of either comparator can set the flip-flop FF1 to
indicate a fault at the open-drain LATCHRPT pin. The fault can be
cleared by setting RPWM3 = 0 to reset flip-flop FF1.
The two comparators are identical but only the output of
comparator 1 (CMP1) is available at the CMP1O pin. CMP1O is a
push-pull output and its output high level is clamped to VDDREF.
The fault detection logic is shown in Figure 20.
CMP2+
CMP2-
CMP1+
CMP1-
CMP1O
CMP2
VDDREF
CMP1
RPWM3
OCP3
ONE
SHOT
S ^SET Q
FF1
R CLR Q
ISL1801
LATCHRPT
FIGURE 20. FAULT DETECTION LOGIC
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FN8259.1
July 24, 2014