ISL1801 Datasheet, PDF (21/30 Pages) Intersil Corporation – sPMIC for Micro Converter Bias and Drivers

ISL1801
The WDI pin is pulled to VDDREF by an internal 40kΩ resistor.
When the WDI pin is floating, the WDI voltage will be VDDREF.
The WDI signal is compared to two threshold voltages resulting in
the periodic discharge of the capacitor on the TIMER pin or
disabling the watchdog function.
The WDI pin voltage is compared to VDDREF/2 to determine if
there is any activity on the pin. Any rising or falling transition on
the WDI pin that crosses the VDDREF/2 threshold will generate a
one-shot pulse to pull the TIMER pin low for 1.5ms.
The WDI pin voltage is also compared to 90% of VCC5V. If the
WDI pin is above 90% of VDD5V the watchdog feature will be
disabled and the TIMER capacitor will not be discharged.
If the WDI pin voltage stays at any constant voltage below the
disable threshold the resistor from TIMER to VCC5V will charge
the capacitor. When the TIMER pin voltage reaches 90% of
VCC5V a time-out event is triggered and PGOOD2 will be set low
for 0.5ms.
Whenever WDI enters or exits its disable mode the TIMER pin is
pulled low for 1.5ms.
VDDREF
ISL1801
TIME-OUT
0.9*VCC5V
VCC5V
40k
R
WDI
R
ONE
SHOT
EN
TIMER
0.9*VCC5V
FIGURE 24. WATCHDOG TIMER LOGIC
It is important to note that the maximum leakage current into
the TIMER pin is 1µA. This leakage current across the pull-up
resistor will set the maximum voltage on the TIMER pin. In order
to assure correct operation, the pull-up resistor from the TIMER
pin to VCC5V should never be more than 200kΩ. The voltage drop
for 1µA across 200kΩ is 200mV, well below the 90% threshold
value of 5V - (5V * 90%) or 5V - 4.5V = 500mV. This is important
because soft-start is initiated by crossing the 90% of VDD5V
threshold and the watchdog timeout also depends on crossing
this threshold.
Figure 25 shows the typical operational waveforms of the
watch-dog timer circuit.
t₀: The VR1/V_OUT1 voltage ramps up to its threshold voltage;
WDI is pulled to VDDREF, which is 0V; TIMER starts to
ramp-up.
t₁: TIMER reaches the 90% threshold (0.9 * 5V = 4.5V) and
starts to initialize the ISL1801.
t₂: All preloads are sequentially applied, reset TIMER and hold
it low for 1.5ms.
t₃: 1.5ms timeout, TIMER starts to ramp up.
t₄: TIMER voltage reaches 90% threshold, release all preloads
and enable VR2 soft-start.
t₅: VR2 finishes soft-start and PGOOD2 goes high; reset TIMER
and hold for 1.5ms, then enable the watchdog function; MCU
starts to run, WDI is floating at VDDREF, TIMER ramps up.
t₆: MCU sends out the first pulse and the WDI falling edge
(from high to low) resets TIMER for 1.5ms; then TIMER
ramps up.
t₇: TIMER is reset for 1.5ms by the WDI rising edge; then
TIMER ramps up.
t₈: TIMER is reset for 1.5ms by the WDI falling edge; then
TIMER ramps up.
t₉: TIMER is not reset in time and reaches 90% threshold level;
PGOOD2 is pulled low for 1ms to reset MCU; and TIMER is
reset for 1.5ms.
t₁₀: PGOOD2 goes back high to exit MCU reset.
t₁₁: 1.5ms timeout, TIMER ramps up.
t₁₂: TIMER is reset for 1.5ms by the WDI rising edge; then
TIMER ramps up.
t₁₃: TIMER is not reset in time and reaches the 90% threshold
level; PGOOD2 is pulled low for 1ms to reset MCU; and
TIMER is reset for 1.5ms.
t₁₄: PGOOD2 goes back high to exit MCU reset; then TIMER
ramps up.
VOUT1
WDI
4.5V
TIMER
0.6*VDDREF
4.5V
PGOOD2
t₀ t₁ t₂ t₃ t₄ t₅ t₆ t₇
t₈
t₉ t₁₀ t₁₁ t₁₂
t₁₃ t₁₄ t₁₅ t₁₆ t17 t18 t₁₉
t₂₀
FIGURE 25. WATCHDOG TIMER WAVEFORMS
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July 24, 2014