ISL1801 Datasheet, PDF (28/30 Pages) Intersil Corporation – sPMIC for Micro Converter Bias and Drivers

ISL1801
discharge path. For example, it is better to allow some extra
distance between the input capacitors and the high-side
MOSFET than to allow distance between the inductor and the
synchronous rectifier or between the inductor and the output
filter capacitor.
• Ensure that the OUT connection to COUT is short and direct.
However, in some cases it may be desirable to deliberately
introduce some trace length between the OUT connector node
and the output filter capacitor.
• Route high-speed switching nodes (BOOT, PHASE, DRIVE3 and
BDRIVE) away from sensitive analog areas (VDDREF, FB and
AMP±). Use PGND1 and PGND2 as an EMI shield to keep
radiated switching noise away from the IC's feedback divider
and analog bypass capacitors.
• Make all pin-strap control input connections to GND or VCC of
the device.
Layout Procedure
Place the power components first with ground terminals
adjacent. If possible, make all these connections on the top layer
with wide, copper-filled areas.
Mount the controller IC adjacent to the synchronous rectifier
MOSFETs close to the hottest spot, preferably on the back side in
order to keep DRIVE3, GND, and the BDRIVE gate drive lines
short and wide. The DRIVE3 gate trace must be short and wide,
measuring 50 mils to 100 mils wide if the MOSFET is 1” from the
controller device.
Group the gate-drive components (BOOT capacitor, VIN bypass
capacitor) together near the controller device.
Make the DC/DC controller ground connections as follows:
1. Near the device, create a small analog ground plane.
2. Connect the small analog ground plane to GND and use the
plane for the ground connection for the VDDREF and VCC
bypass capacitors, FB dividers and ILIM resistors (if any).
3. Create another small ground island for PGND and use the
plane for the VIN bypass capacitor, placed very close to the
device.
4. Connect the GND and PGND planes together under device.
On the board's top-side (power planes), make a star ground to
minimize crosstalk between the two sides. The top-side star
ground is a star connection of the input capacitors and
synchronous rectifiers. Keep the resistance low between the star
ground and the source of the synchronous rectifiers for accurate
current limit. Connect the top-side star ground (used for MOSFET,
input, and output capacitors) to the small island with a single
short, wide connection (preferably just a via). Create PGND
islands on the layer just below the top-side layer to act as an EMI
shield if multiple layers are available (highly recommended).
Connect each of these individually to the star ground via, which
connects the top-side to the PGND plane. Add one more solid
ground plane under the device to act as an additional shield, and
also connect the solid ground plane to the star ground via.
Connect the output power planes directly to the output filter
capacitor positive and negative terminals with multiple vias.
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FN8259.1
July 24, 2014